Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

system-verilog system-verilog-assertions system-verilog-dpi uvm vpi icarus iverilog verilator

6035 questions

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1 answer

Interface to an8-digit seven-segment display

I'm supposed to interface to an 8-digit seven-segment display This is how the circuit looks like: And here's my code: `timescale 1ns / 1ps module TimeMUXDisplay(input clk,input [5:0] DIN, output reg [7:0] E,output reg [6:0] C,output…

verilog

asked May 08 '16 at 15:46

Jack

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2 answers

What's the general procedure for compiling an HDL Program for an FPGA?

I have a question regarding the compilation of HDL programs within the context of FPGA design. 1) Why does the compilation process take so long? Is it really the compilation process that takes a long time, or is it the writing of individual logic…

vhdl verilog fpga system-verilog hdl

asked May 04 '16 at 23:11

Izzo

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2 answers

Can I call a VHDL function inside Verilog

I am currently trying to use certain legacy VHDL codes into my Verilog design. While it is possible to instantiate VHDL modules within Verilog, I could not find a way to call VHDL functions within Verilog. (Apart from wrapping it around in a VHDL…

vhdl verilog system-verilog

asked Apr 21 '16 at 02:25

Pulimon

1,776
4
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45

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1 answer

Is there any recommended way to automate module port connection?

I'm trying to understand or research about the best practices of ASIC design in verilog. I'm working on a medium size block with ~20 sub modules (each ~1000 lines of code). It's a painstaking job to manually instantiate all the sub-module and do…

automation verilog system-verilog

asked Apr 08 '16 at 01:58

newbie

4,639
10
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1 answer

Usage of Clocking Blocks in Systemverilog

What is the exact usage of Clocking Blocks in System Verilog, and how does it differ from normal always @ (posedge clk) block? Some differences, which I know : Clocking Block samples input data from Preponed Region, whereas in normal always…

verilog system-verilog

asked Oct 04 '15 at 15:06

Karan Shah

1,912
1
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42

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8 answers

Why does the chip control the language to choose

I've asked the question before what language should I learn for embedded development. Most embedded engineers said c and c++ are a must, but also pointed out that it depends on the chip. Can someone clarify? Is it a compiler issue or what? Do chips…

c++ c embedded verilog

asked Jul 18 '10 at 05:43

cooper

1,554
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2 answers

What are the uses of force - release statements?

From a hardware point of view, what do force and release statements model? What are the uses of these statements?

verilog system-verilog

asked Jul 11 '15 at 09:38

pradeep

3,005
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42
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2 answers

Doxygen alternative for Verilog, SystemVerilog?

Project "doxverilog" is not supported more, author's site is not responding. Project http://intelligentdv.com/downloads/index.html#doxygentools works only for SV class hierarchy. AMIQ http://www.dvteclipse.com/ Specador is enterprise overpriced…

verilog doxygen fpga system-verilog asic

asked Apr 22 '15 at 12:07

Mike I.

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1 answer

Parameter inside a module inside a module

I have read about parameters and how to redefine them at module instantiation, but what if I have a parameter inside a module inside a module? Say that I have a small module called gen: module gen(input,output); parameter n=2; parameter m=10; //do…

verilog

asked Feb 25 '15 at 23:02

Ahmed Salah

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2 answers

Mixing blocking and non-blocking assign in Verilog (or not!)

I'm implementing a simple serializer in Verilog, but I do not understand the nuances of when blocking assigns can cause problems. I'm specifically having trouble understanding part of this answer. "However, you should never use blocking assignments…

verilog

asked Feb 19 '15 at 05:10

Pete Baughman

2,996
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3 answers

Is there a way to define something like a C struct in Verilog

I have a project, written in Verilog (importantly not SystemVerilog) which has gotten a little unmanageable due to the number of signals being passed along between different parts of the design. Since I have several modules which all need the same…

struct verilog hdl

asked Dec 16 '14 at 18:23

seanmk

1,934
15
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6 answers

Should you remove all warnings in your Verilog or VHDL design? Why or why not?

In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry…

verilog vhdl system-verilog fpga asic

asked Apr 27 '10 at 15:01

Brian Carlton

7,545
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1 answer

How to write a testbench to loop through 4 inputs?

I have to create the Verilog code and testbench for this schematic. I have the design for it here. module prob1(input wire a,b,c,d, output wire out); assign out = (a||d)&&(!d&&b&&c); endmodule Here is what I have for the testbench so…

loops testing verilog system-verilog

asked Oct 05 '14 at 20:42

user2680027

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1 answer

test bench for writing verilog output to a text file

i am unable to get correct output in a text file however simulation in modelsim is quite ok.. but while writing it to text file im getting XX for every input. may be there is some syntax error or some other. if any can help plz write down test bench…

verilog vlsi

asked Sep 01 '14 at 13:39

user3432905

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2 answers

Parameter array in Verilog

Is it possible to create a parameter array in Verilog? For example, anything like the following: parameter[TOTAL-1 : 0] PARAM_ARRAY = {1, 0, 0, 2} If it is not possible, what could be the alternative solution?

verilog hdl

asked May 07 '14 at 02:21

user3610437

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