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Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

Class library for .

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

  • UVM User's Guide 1.1
  • UVM User's Guide 1.2
  • IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)
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UVM- run test() in top block and Macros

I'm reading the following guide: https://colorlesscube.com/uvm-guide-for-beginners/chapter-3-top-block/ In Code 3.2 line 24- run_test(); I realized that it supposed to execute the test, but how it know which test, and how, and why should I write it…
sara8d
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What to do in case of multiple producer and single consumer?

While developing test bench you might face a situation of multiple producers and a single consumer. e.g. Single Scoreboard (consumer) receives data from the driver and monitor (multiple producers). How to send data from multiple producers to…
Ashutosh Rawal
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Generate random enum using system Verilog

typedef enum int { IPV4_VERSION = 0, IPV4_IHL = 1, IPV4_TOTAL_LENGTH = 2,IPV4_CHECKSUM = 3 } ipv4_corrupton; ipv4_corrupton ipv4_corrupt; std::randomize(ipv4_corrupt) with {ipv4_corrupt dist { IPV4_VERSION :=2,IPV4_IHL := 4,IPV4_TOTAL_LENGTH :=…
Saravanan Shanmugavelu
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setting the Verbosity only for few /sequences/objects/interfaces in uvm?

How do I control the verbosity of certain components so that I can set a verbosity to only few of the components? Lets say, for example in the verification of a particular feature, the test, few set of components/sequences/objects/interfaces etc are…
Vineeth VS
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difference between std::randomize and class based randomize

What is the difference between option A and Option B Option A: sucess = std::randomize(type_l) with { type_l inside { A ,B ,C}; type_l dist { A := 2 ,B := 5 ,C := 4 }; }; if( sucess == 0 ) begin `uvm_fatal("TEST_CFG", "type_l…
Saravanan Shanmugavelu
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How is backdoor access for registers, physically implemented in a VLSI design?

Synthesizable register(s) can conventionally be verified using access technique that use address & data buses (these buses are very much part of the actual hardware present on the silicon chip). But this conventional access technique consumes finite…
Anand
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'this' equivalent for SystemVerilog interfaces

Is there an equivalent construct to this for SystemVerilog interfaces? What I'd like to do is a bind of an interface inside some DUT block and then pass it using the UVM config DB as a virtual interface: bind some_block…
Tudor Timi
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Regex in SV or UVM

What functions do I need to call to use Regular Expressions in Systemverilog/UVM? Note: I'm not asking how to use regular expressions, just method names.
Karan Shah
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Disabling a scoreboard from a sequence using UVM

I have a uvm_sequence that randomizes an enable bit "feature_en". Depending on whether this bit is enabled or not, I want to enable/disable my scoreboard. I use the config_db to set the variable, and the field_macros to automatically get it in the…
noobuntu
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How to use UVM factory's set_inst_override_by_name to override sequence item

I have two sequence item class a_packet and its extended class called bad_packet. By default, a_packet type is used. Trying to override a_packet instance with bad_packet, I am able to do it successfully by using set_inst_override_by_name in my uvm…
AldoT
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What is the meaning of an object of the class inside it's class-endclass definition?

What is the meaning of the following code (2nd line) in which inside class uvm_resource_pool definition, instance (object) rp is created? class uvm_resource_pool; static local uvm_resource_pool rp = get(); // Function: get // // Returns…
Karan Shah
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connecting VHDL port to system verilog interface definition in UVM

I am having this issues in the Cadence tool chain simulation when I try to connect the multidimensional user defined type in VHDL to SystemVerilog in a UVM environment. This is the VHDL output type definition: TYPE loop_reg_ty IS RECORD …
user2293385
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Grab Transactions inside UVM_Sequencer Run Phase

I want to grab the transactions inside my uvm_sequencer's run_phase to check if the transactions are crossing 4KB boundary. In case they cross the 4KB boundary I want to split that transaction into multiple transactions and then send it to the…
sundar
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UVM_INFO returning a HEX value

I use this command to print the contents of the transaction class in Questasim: `uvm_info("VALUES", tx.sprint(), UVM_LOW) My transaction has a variable ans. The problem is it is printing it as HEX rather than DECIMAL. It shows: ans integral …
Vineeth
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System Verilog interface with different inputs

I have defined an interface for my DUT as such: interface video_input_interface(clk, rst); input logic clk; input logic rst; logic[1:0] x_lsb; logic[1:0] x_msb; logic[3:0] x; assign x = {x_msb,…
noobuntu
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