Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

UVM User's Guide 1.1
UVM User's Guide 1.2
IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)

527 questions

votes

1 answer

Functional Coverage - bin that collects all values that are not collected in other bins

ipv6_hdr__f_next_header_cp: coverpoint this.ipv6_hdr.ipv6_f_next_header iff (this.has_ipv6_header){ bins ipsec_33 = {'h33}; bins tcp_06 = {'h06}; bins udp_11 = {'h11}; bins done_3b = {'h3b}; bins ipv6_ext_any_other [3] =…

asked Jan 12 '21 at 16:22

Yakir Yehudai

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1 answer

UVM DPI-C function import

Can somebody please educate me why we need DPI-C function import to do UVM specific functions like uvm_hdl_force or uvm_hdl_deposit even when force and deposit system verilog constructs exist? What extra flexibility does the C functions give with…

system-verilog uvm system-verilog-dpi

asked Sep 21 '19 at 22:05

user1978273

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2 answers

Is there a way to connect uvm_tlm_analysis_fifo to uvm_driver?

I need to connect a module output to it's input controlled by uvm_driver. I see it this way. ----- --------------------- | MON |---->|uvm_tlm_analysis_fifo| ----- …

system-verilog fifo uvm

asked Jul 16 '19 at 09:25

Андрей Солодовников

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1 answer

Compiling verilog packages with same name

Verilog 2K has support for compiling modules with different implementation using the "config" facility. In my multi chip uvm env I need to use 2 different packages(chip_top_pkg.sv) which have exactly the same name but different uvm components. Is…

system-verilog uvm

asked Dec 04 '18 at 05:20

Sanjeev Singh

votes

3 answers

uvm_component parent in the class constructor

One thing that always confuses me: is whether add uvm_component parent in the class constructor of UVM objects or not. As I understood for all items inherited from uvm_component, they all need uvm_component parent as part of constructor input…

uvm

asked Jan 11 '18 at 02:19

haykp

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1 answer

How to change uvm verbosity for an object in component

I encountered an issue when setting verbosity for an object in component. I want to set the verbosity of specific components (uvm_test_top.env.subenv_a) to UVM_HIGH, command line argument is as…

system-verilog uvm

asked Nov 27 '17 at 08:07

ken

votes

1 answer

How to attach an UVM sequence with a particular sequencer?

I have 3 sequences, and 4 sequencers. I want sequencer 1 to run sequence1, sequencer 2 to run sequence1, sequencer 3 to run sequence2, sequence3 in serial order. sequencer 4 to run sequence1, sequence2 in serial order. One method to do so is…

system-verilog sequences uvm

asked Aug 19 '17 at 07:59

Shankhadeep Mukerji

votes

2 answers

Cant see assertions/ functional coverage in the environment

I used the covfile and select_functional command in the running options of the regression, and the coverage groups appear, but I can't see the assertions in IMC in order to map them. If I run a test and give the covfile command it works, but on…

code-coverage system-verilog uvm

asked May 18 '17 at 07:45

Madalina Gheboianu

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2 answers

What would be the best method to check frequencies of clocks that has a +/- tolerance %?

Below is the property that I currently use. property freq_chk (time clk_period , bit disable_chk=0); time current_time; disable iff ( disable_chk ) ('1, current_time = $time) |=> ( (($time - current_time) >= (clk_period-1)) && …

system-verilog uvm system-verilog-assertions

asked May 11 '17 at 12:55

Vineeth VS

votes

1 answer

uvm_reg_predictor predict not working

In my environment, I have connected predictor bus_in port to output analysis port of monitor. I have also implement reg_adapter bus2reg function and connect adapter to predictor. I'm using passive prediction…

verification uvm

asked May 09 '17 at 18:03

lrx2009

votes

1 answer

Importing systemverilog package as another name

Is there a mechanism to import a systemverilog package as another name, similar to what is available in Python? I have a package I need to import, and the name of the package is top_pkg. I want to import it as subsystem_pkg

system-verilog uvm

asked Apr 26 '17 at 20:45

noobuntu

votes

1 answer

Huge lookup table in SV/UVM

I have to build a big lookup table (~14k entries with strings as keys) by parsing an input file for a predictor. Am I better off using an associative array or use uvm_config_db from simulation performance point of view?

uvm

asked Feb 28 '17 at 21:40

vivek

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1 answer

Specman UVM Scoreboard basic questions

I've built the next (working correctly) Scoreboard/Monitor environment: // Scoreboard : like uvm_scoreboard scbd_port packet_add : add packet_s; scbd_port packet_match : match packet_s; My ADD flow: // Monitor: expected_packet_o : out…

uvm specman e

asked Jan 30 '17 at 12:34

Halona

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2 answers

Assertion module in an UVM testbench

I have written an UVM testbench that has 3 agents and am now in the process of writing a scoreboard/checker. I need to have a checker module for my SystemVerilog Assertions, but this checker module needs to be aware of register configuration that is…

system-verilog uvm

asked Oct 14 '16 at 22:09

noobuntu

votes

1 answer

What are the necessary properties in read/write axi transaction?

I am writing a verification environment for a design which includes an AXI bus. What are the necessary properties in the read/write AXI transactions? My transaction looks as seen below. Do I have to add something else? typedef enum bit [3:0] {…

system-verilog uvm

asked Aug 23 '16 at 09:06

sara8d

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