Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

UVM User's Guide 1.1
UVM User's Guide 1.2
IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)

527 questions

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2 answers

uvm_field_* macros - how do I set my custom struct

I can't find a uvm_field_* macro that I can use in my testbench. I defined a struct: typedef struct { unsigned byte red; unsigned byte green; unsigned byte blue; } pixel; Now, in my sequence item, I declare: rand pixel unsigned…

system-verilog uvm

asked May 28 '14 at 15:04

noobuntu

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2 answers

Using burst_read/write with register model

I've a register space of 16 registers. These are accessible through serial bus (single as well as burst). I've UVM reg model defined for these registers. However none of the reg model method supports burst transaction on bus. As a workaround I can…

system-verilog uvm

asked Apr 17 '14 at 21:30

wisemonkey

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1 answer

Basic UVM sequence simulation query

I have a couple of issues with a basic UVM based TB I'm trying out to understand sequences and their working. bvalid is being always picked as 0 in the driver when being updated in the response item Couple of error messages for last 2 transactions…

system-verilog uvm

asked Apr 14 '14 at 04:00

venkstart

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3 answers

How to control the order of UVM analysis port subscribers?

I have an analysis port connected to 3 scoreboards. When a write is done on the analysis port, the subscribers (scoreboards) are called in a certain order. But I want them to be called in a different order. The practical use case for explicit…

system-verilog uvm

asked Apr 09 '14 at 12:52

Victor Lyuboslavsky

9,882
25
87
134

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3 answers

How to perform uvm_do_on without randomization?

I have a virtual sequencer from which I execute three transactions in parallel, each one on its corresponding sequencer. So I have something like this: class top_vseqr extends uvm_seqr extends uvm_sequencer; type_a_seqr seqr_a; type_b_seqr…

uvm

asked Mar 07 '14 at 16:08

eSedano

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3 answers

What does warning about trying to predict while register being accessed means?

I've UVM verification environment. In my test sequence I read (mirror) from REGA through FRONTDOOR (serial transaction) upon receiving interrupt. In my scoreboard I've used .predict methods to updated expected values of REGA. However I've following…

system-verilog uvm

asked Mar 05 '14 at 22:07

wisemonkey

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1 answer

Register virtual class with UVM factory

Does anyone have a way of registering virtual classes with the factory? Using the object_utils macro will define the type_id::create(...) method which calls new(...) for the virtual class which is illegal. Naturally, a type override would be…

system-verilog uvm

asked Mar 05 '14 at 10:44

Tudor Timi

7,453
1
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53

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1 answer

UVM phase singletons

After browsing a bit through the UVM source code, I noticed that singletons for each phase exist. For the run phase this can be accessed by calling uvm_run_phase::get(). I tried calling uvm_run_phase::get() from both the run_phase and the…

system-verilog uvm

asked Feb 28 '14 at 15:44

Tudor Timi

7,453
1
24
53

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2 answers

SystemVerilog: registering UVM test with the factory

I am confused with the following SystemVerilog construct used for registering the UVM test with the factory: class random_test extends uvm_test; `uvm_component_utils(random_test); ... function new (... Here we have a definition of the…

class factory system-verilog uvm

asked Feb 25 '14 at 16:07

jazzblue

2,411
4
38
63

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1 answer

How to print the whole queue/array with UVM utility functions?

For UVM objects using `uvm_field_queue_int utility macro, UVM does not print out the whole queue when calling my_object.print() # ----------------------------------------- # Name Type Size Value # ----------------------------------------- #…

printing queue system-verilog uvm

asked Feb 11 '14 at 18:34

Victor Lyuboslavsky

9,882
25
87
134

votes

3 answers

Can UVM flag a bad command line argument?

I'm using UVM command line arguments to set configuration properties in the UVM hierarchy. When I pass in a bad config option, I would like to see a UVM_ERROR or another failure indication. What's the easiest way to accomplish this? For example, if…

command-line-arguments system-verilog uvm

asked Dec 19 '13 at 18:03

Victor Lyuboslavsky

9,882
25
87
134

votes

1 answer

SystemVerilog macros not needing a ';' at the end of a line

In SystemVerilog, it is not required to add a ';' at the end of a line. For example: `uvm_do(pkt) I wonder why the compiler can handle this, but can't handle regular lines without the ';'.

verilog system-verilog uvm

asked Nov 14 '13 at 09:36

Nadav

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2 answers

Strategy to share signals between predefined UVCs

I'm trying to figure out how to connect multiple UVCs (UVM Verification Components) to the same DUT where the UVC's do not share an interface but do connect to the same signals on the DUT. The DUT that can operate on different protocols on common…

system-verilog uvm

asked Nov 07 '13 at 01:31

Greg

18,111
5
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1 answer

I am trying to understand the way I can write a UVM scoreboard for a DUT (arbiter) with multiple masters and one slave

I need to write a scoreboard for a DUT which has 3 AXI masters as input and one of them goes out on the other side to AXI slave, like 3 AXI masters-> DUT-> AXI slave. Please let me know if my understanding below is correct or are there any more ways…

system-verilog verification uvm amba

asked Aug 23 '23 at 08:53

Grace90

vote

1 answer

Multi-master AXI interface connections

Do we need to have three instantiations of AXI master interface in top file if we have 3 AXI masters and then send these three interfaces to 3 AXI agent instantiations using the config_db? Or, how does it work in case of a multi-master scenario to…

system-verilog uvm test-bench amba

asked Aug 23 '23 at 08:29

Grace90

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