I am writing a verification environment for a design which includes an AXI bus.
What are the necessary properties in the read/write AXI transactions?
My transaction looks as seen below. Do I have to add something else?
typedef enum bit [3:0] { LENGTH_[1:256] } length_e;
//----------------------------------------------------------------------
//Transaction
//----------------------------------------------------------------------
class axi_transaction extends uvm_sequence_item;
bit [3:0] id;
bit [31:0] address;
length_e length;
transfer transfers[];
int unsigned delay;
endclass
class transfer extends uvm_sequence_item;
rand bit[31:0] data;
rand int unsigned delay;
// ...
endclass