Concatenation operator in System verilog in a loop

Question

I am trying to do the following : concat = {concat[7:0],clk} inside a forever loop as below :

   bit [7:0]    concat;
   concat = 0;
   forever begin
        @(posedge clk);
        concat = {concat[7:0],clk};
    end

I wanted to know what value will it contain after 8 clock iterations at any point of time, if the initial value of concat = 0.

Can it be different from 'hAA or 'h55 at any point of time?

score 1 · Answer 1 · edited Sep 24 '14 at 13:35

1

You can not just write concat = 0; you should either assign concat = 0; or

initial begin
  concat = 0;
end

Forever can not be used like that, the only two top levels you're allowed are initial and always. You want some thing like the following for a simulation:

initial begin
  forever begin
    @(posedge clk);
    concat = {concat[6:0],clk};
  end
end

If you are writing for synthesis then you might want to imply a flip-flop:

always @(posedge clk) begin
  concat = {concat[6:0],clk};
end

Once you have fixed your RTL it should be easy to try out on EDA Playground.

edited Sep 24 '14 at 13:35

Chiggs

2,824
21
31

answered Sep 24 '14 at 12:06

Morgan

19,934
8
58
84

Thank you for replying Morgan. Assume that everything is fine, the above (similar)piece of code is used in a UVM testbench. I just wanted to know what would be the output because I am not able to debug this using uvm_info macro as it is being used in an if condition which is not occurring. Any pointer would be appreciated – user3714538 Sep 24 '14 at 14:08
@user3714538 The block only triggers or waits for on `posedge of clk` ie clk is 1. Therefore concat will slowly fill up with 1's, after 8 clks will always be `FF`. – Morgan Sep 26 '14 at 06:43

score 0 · Accepted Answer · answered Sep 24 '14 at 15:40

Since you have @(posdege clk), clk will always be 1 (or x) when evaluating the RHS of the assignment. So concat will be 'h00, 'h01, 'h03, 'h07, 'h17, ...

Also note that if any other thread tries to read concat on the same positive edge of clk, you have a race condition, so please use a NBA to make the assignment.

Concatenation operator in System verilog in a loop

2 Answers2