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Questions tagged [synopsys-vcs]

Synopsys VCS Verilog Simulator

From Wikipedia:

Originally developed by John Sanguinetti, Peter Eichenberger and Michael McNamara under the startup company Chronologic Simulation, VCS (Verilog Compiled code Simulator) was purchased by Synopsys, where development continued. Due to a strategic decision to support SystemVerilog (instead of SystemC), and the acquisition of Superlog (the forerunner to SystemVerilog), Synopsys/VCS was the first SystemVerilog simulator in the market. Supports simulation of designs written in VHDL as well.

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Synopsys VCS message severity change from warning to error

I want to change the severity of a VCS message from warning to error. E.g.: Warning-[TMR] Text macro redefined I want to change TMR to Error severity instead of warning. Please suggest me a way of doing this. Where am I supposed to do this setting?
PRASHANTH N
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how to get power estimation using xpower

I have been working on a class project using Verilog. I had to create a circuit and then calculate the power that the circuit uses. I have been trying to do it using Xpower Analyzer I follow the instruction to create the vcd file, compile and…
Adonis H.
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Parameterized class declaration error in UVM

I'm trying to use a parameterized class extended from uvm_object. class som_util #(int entry_w=2) extends uvm_object; `uvm_object_utils(som_util) "Some other static functions using the parameterized variables" endclass When I run my tests on IUS…
seek
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Net 'VectorY[0]', or a directly connected net, is driven by more than one source, and at least one source is a constant net. (ELAB-368)

I am getting this error in VCS synthesizer. I have tried everything but it doesn't make sense to me. it says VectorY[0], VectorY[1], VectorY[2], VectorY[3], or a directly connected net, is driven by more than one source, and at least one source is a…
Aliyar Attaran
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SystemVerilog over vcs saving simulation state and rewinding

I am running a testbench using systemverilog over OVM using vcs. I want to save my simulation after some reset phase and then return to it later on in the test, or/and from another testbench. Is this possible using systemverilog cmds? Alternatively…
ronenmiller
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Synopsys: get the total number of paths in the circuit

I'm working with dc_shell of Synopsys and I'm trying to obtain the total number of paths of the synthetized circuit with a slack lesser than to a particular value. In order to do that I'm using the command: get_timing_paths -slack_lesser_than…
linux91
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low power circuit design in verilog and calculate power for different input sequences

I want to implement the following circuit in verilog. FA is the full adder circuit and trapezoidal shape is a mux. I am not sure how to add this power gating pmos in the circuit. And also I would like to synthesize the circuit in Synopsys Design…
Snigdha203
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Inconclusive Assertion in Synopsys VC Formal

2 Questions - In Assertion Based Formal Verification, if I get an Inconclusive Assertion, then what are the various approaches to handle that assertion or to converge it? Is it a right approach to develop a reference rtl and write assertions to…
Karan Shah
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Combination of 2 commands in TCL

Here are the results of some TCL commands. get_props -type assert {"a", "b", "c", "d"} Now all these 4 objects have certain attributes associated with them. But I am interested in the "enabled" attribute only. get_attribute [get_props a]…
Karan Shah
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synopsys dc_shell get_attribute number of digits

In order to perform some optimizing algorithm, I need a good degree of precision in getting attributes from tcl dc_shell (synopsys Version D-2010.03-SP3). For example get_attribute CORE65LPLVT/HS65_LL_IVX9 cell_leakage_power returns me 0.000001…
marco6
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How do I fix "Error-[ICPSD] Invalid combination of drivers"?

I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions. **The errors I am receiving are: Error-[ICPSD] Invalid combination of drivers Variable "Q" is driven…
codewarrior453
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VCS incremental elaboration feature

Does anyone knows this feature? I came across this term, and not sure this is not the same as incremental compilation (below) .... 4 modules and 0 UDP read. However, due to incremental compilation, only 1 module needs to be…
Avi Farjoun
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Verilog always vs assign

Is it legal for a simulator to evaluate clk_out1 in the next active Verilog scheduling window w.r.t clk? clk_out2 seems to be updated in the same scheduling window as clk. reg clk_out1; always @(*) clk_out1 = clk; assign clk_out2 = clk; In…
Jean
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What is -quiet in TCL

I need what below if statement gives true or false, Also please explain about "quiet" if {[sizeof_collection[get_pins $source-quiet]]>0} What is gives? Note:- $source is I_TEST_MODE4.
Prafull Kumbhar
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How to display list of Verilog force from Modelsim / Synopsys simulator?

For the ncsim https://community.cadence.com/cadence_technology_forums/f/functional-verification/17382/ncsim-how-to-display-list-of-verilog-force-from-inside-verilog-testbench. How to track the list of Verilog force, is there any simulator/language…
Mana
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