How do I fix "Error-[ICPSD] Invalid combination of drivers"?

Question

I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions.

**The errors I am receiving are:

  Error-[ICPSD] Invalid combination of drivers
  Variable "Q" is driven by an invalid combination of structural and 
  procedural drivers. Variables driven by a structural driver cannot have any 
  other drivers.
  "divide.v", 13: logic [7:0] Q;
  "divide.v", 16: divide8bit testcase1(x, y, clk, Q, R);
  "divide.v", 23: Q = 8'b0;

  Error-[ICPSD] Invalid combination of drivers
  Variable "R" is driven by an invalid combination of structural and 
  procedural drivers. Variables driven by a structural driver cannot have any 
  other drivers.
  "divide.v", 13: logic [7:0] R;
  "divide.v", 16: divide8bit testcase1(x, y, clk, Q, R);
  "divide.v", 24: R = y;

**My SystemVerilog Code is:

module divide8bit(
  input logic [7:0] x,y,
  input logic clk,
  output logic [7:0] Q,R);

  always_ff @(posedge clk)
    begin
      R <= R-x;
      Q <= Q + 8'd1;
    end
endmodule

module test1;

  logic [7:0] x,y,Q,R;
  logic clk;

  divide8bit testcase1 (x,y,clk,Q,R);

  initial 
    begin
            x = 8'd2;
            y = 8'd8;
            Q = 8'd0;
            R = y;
            clk = 1'd0;
            while(x <= R)
                begin
                    #5 clk = ~clk;
                end
            #5 $finish; 
        end
endmodule

I find the question more readable when separating the testharness from the DUT. Smaller distinct code blocks I find easier to parse and understand the hierarchy, this might be worth considering for future questions. — Morgan, Sep 22 '14 at 09:09

score 1 · Accepted Answer · edited May 23 '17 at 12:12

1

Same problem here: you are assigning to Q and R inside module test1. At the same time module testcase1 is also trying to assing to Q and R. Don't assign to Q and R in test1!

edited May 23 '17 at 12:12

Community

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1

answered Sep 21 '14 at 05:15

Ari

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How would you go about assigning them at the beginning and delaying the always. That is my only problem. I've been at it for hours over this problem. The thing about making all my initializations in an always loop is, it will repeat and I only need them to start at Q=0 and R=y once. – codewarrior453 Sep 21 '14 at 05:18
1

You are implementing Q and R to behave as a flop, which can be initialized using a reset signal. Use a flop with async reset: http://www.asic-world.com/examples/verilog/d_ff.html – Ari Sep 21 '14 at 05:21

How do I fix "Error-[ICPSD] Invalid combination of drivers"?

1 Answers1