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Questions tagged [synopsys-vcs]

Synopsys VCS Verilog Simulator

From Wikipedia:

Originally developed by John Sanguinetti, Peter Eichenberger and Michael McNamara under the startup company Chronologic Simulation, VCS (Verilog Compiled code Simulator) was purchased by Synopsys, where development continued. Due to a strategic decision to support SystemVerilog (instead of SystemC), and the acquisition of Superlog (the forerunner to SystemVerilog), Synopsys/VCS was the first SystemVerilog simulator in the market. Supports simulation of designs written in VHDL as well.

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Viewing enum names in vcs ucli

I am working in VCS UCLI (ie, the command line interface) and am having trouble getting VCS to display various state variables, of a typedef'd enum type, value as the name rather than the number. For example, I have some SystemVerilog like…
Unn
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Checking for amount of open files while running SystemVerilog testbench

I am running a test to compare output data of the system to a set of golden data generated on a text file, but when the test runs to around 2000 frames +, I start getting an error where is says: warning-Cannot open file file could not be opened.…
miner_kai
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How to make Synopsys VCS Verdi to show display macro messages in Wave window?

I know that in Questa or Riviera UVM error messages can be indicated in the waveform as well. With system verilog display macros (but not UVM!), how can an indicator be shown in the Synopsis Verdi waveform when the display happens? For example lets…
Magor Keszthelyi
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I am trying to form a rectangle with 2 pairs of Coordinate in TCL

I am new to TCL and hardware design. I am currently doing a script that could verify all the ports at an edge and make a rectangle box that cover all the ports at an edge. Since I am new to TCL, I think there is something wrong in the syntax. The…
Kavin Raj
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Fusion Compiler IO filtering command - Tcl

i am currently learning about IC physical design. I came across this set of TCL command which I understand only partially. I the second and third 'set' command, what does the '-only_leaf' and '-flat' refer to? Please help me by giving some…
Kavin Raj
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Running a command on multiple files using TCL script

I am using a certain tool (Synopsys Design Vision) which I am running by using a TCL script. The command is something like this analyze -library work -format verilog {/user/codes/abcd.v } Now I have a folder with 5000 .v extension files with names…
avi1987
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Copy signal value in DVE

I'm using Synopsys DVE simulator and want to copy value from the waveform window, but I cannot find any button or option to do this. Ctrl+C copies the full path of the signal, but not the current value of the signal. The DVE user guide does not…
MitsuiYang
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SystemVerilog Concurrent Assertion Sequence Dynamic Length

I have an array of length x. A signals output for a given testbench will be each value in the array in its respective order from 0:x-1. In my problem in particular, the array is filter coefficients and the testbench is the impulse response. The test…
Daniel
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How to prevent segmentation fault of concurrent jobs in Bazel?

I wrote a rule to run some compiler (Synopsys VCS MX). When running a single target, everything works great. When running multiple targets concurrently, the compiler runs into a segmentation fault. This doesn't happen when running Bazel with…
Erran
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In synopsys VCS, how can I get the raw RTL verilog output file?

I need the VCS preprocessor output. Theres a way to get a verilog file where all params and macros are filled in from the preprocessor. How do I do that?
user5888527
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Cadence IUS simulator options

What is the difference between -INcdir and +incdir+ options in NC simulator? Below is the example command from the Makefile. As far as I know the testbench directories are included using -INcdir and the source code file directories are included…
Sreejin TJ
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gui_sg_addsignal : How to create generic module hierarchy for signals in a group for Synopsys DVE?

I want to create a signal group with generic TOP name in session file for Synopsys DVE. My purpose is to use the same tcl file for block and system level debugs by defining correct 'TOP' value. set TOP "TOP.Block_level" #set TOP…
SolExplore
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How can I use Synopsys VCS for dynamic voltage scaling in a micro processor?

I'm trying to simulate a RISCV based processor on Synopsys VCS with RTL design (verilog). I would like to change the voltage dynamically while the simulation is running. Is there any tool in Synopsys that can be used for performing dynamic voltage…
deadpool3
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How do I print (put in a log) signal values in a Tcl script running under Synopsys DVE?

I need to extract some values from SystemVerilog data structures after I run the simulation. I would like to do this without changing SystemVerilog code. Below is an example of TCL script I am using in Synopsys DVE environment to add certain…
Yuri Panchul
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Is it possible to fully compile a module and then instantiate it in a testbench separately?

Is it possible to make a fully compiled and standalone version of an RTL module, like a snapshot in Cadence terms, and then later instantiate this compiled module into a testbench? Ultimately, running another compile step to create a final snapshot…
Ginty
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