Verilog always vs assign

Question

Is it legal for a simulator to evaluate clk_out1 in the next active Verilog scheduling window w.r.t clk? clk_out2 seems to be updated in the same scheduling window as clk.

reg clk_out1;
always @(*)
    clk_out1 = clk;

assign clk_out2 = clk;

In this image Red - NBA region Yellow - Active region

Updated with waveform. Question is why there is a mismatch in how VCS is evaluating `clk_out1` and `clk_out2` — Jean, Apr 01 '21 at 00:56
the out2 signal should *not* be updated in the nba region. It needs to be assigned with <= for that. This could be a result of an optimization though. Both out1 and out2 shoudl be evaluated in the active region which follows the #0 and nba region.There could be as many active regions as needed to evaluate all outsanding events. — Serge, Apr 01 '21 at 02:20

score -1 · Answer 1 · answered Apr 01 '21 at 03:46

The Verilog scheduling semantics dictate that both assignments happen in the same active scheduling region. They will behave as if clk, clk_out1 and clk_out2 are aliases for each other. This is assuming you used a regular blocking assignment and not a non-blocking assignment to clk_out1, which is the recommended way of assigning clocks in RTL.

Verilog always vs assign

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