Net 'VectorY[0]', or a directly connected net, is driven by more than one source, and at least one source is a constant net. (ELAB-368)

Question

I am getting this error in VCS synthesizer. I have tried everything but it doesn't make sense to me. it says VectorY[0], VectorY[1], VectorY[2], VectorY[3], or a directly connected net, is driven by more than one source, and at least one source is a constant net. (ELAB-368)

module control (clk, start, S1S2mux, newDist, CompStart, PEready, VectorX, VectorY, addressR, addressS1, addressS2,completed);

    input clk;
    input start;
    output reg [15:0] S1S2mux;
    output reg [15:0] newDist;
    output CompStart;
    output reg [15:0] PEready;
    output reg [3:0] VectorX,VectorY;
    output reg [7:0] AddressR;
    output reg [9:0] AddressS1,AddressS2; 
    reg [12:0] count;
    output reg completed;
    integer i;

    assign CompStart = start;

    always @(posedge clk) begin
        if(start==0) begin 
            count<= 12'b0; 
            completed<=0; 
            newDist<=0;
            PEready<=0;
            VectorX<=0;
            VectorY<=0;
        end
        else if (completed==0) 
            count <= count+1'b1;
    end

    always @(count) begin
        for (i = 0; i < 15; i = i+1)
        begin 
            newDist [i] = (count [7:0] == i);
            PEready [i] = (newDist [i] && !(count < 8'd256));
            S1S2mux [i] = (count [3:0] > i);
        end
        addressR = count [7:0];
        addressS1 = (count[11:8] + count[7:4] >> 4)*5'd32 + count [3:0];
        addressS2 = (count[11:8] + count[7:4] >> 4)*4'd16 + count [3:0];
        VectorX = count[3:0] - 4'd7;
        VectorY = count[11:8] >> 4 - 4'd7;
        completed = (count == 4'd16 * (8'd256 + 1));
    end
endmodule

score 0 · Answer 1 · answered Oct 23 '16 at 02:57

You can probably do like this...in systemverilog

create another logic variable

logic [3:0] VectorY_next;

and then in the sequential block, do ..

always_ff begin
        if(start==0) begin 
            count<= 12'b0; 
            completed<=0; 
            newDist<=0;
            PEready<=0;
            VectorX<=0;
            VectorY<=0;
        end
        else if (completed==0) begin 
            count <= count+1'b1;
            VectorY <= VectorY_next;
        end
end

And in the combinational block, you can write ...

always_comb begin
        VectorY_next = VectorY;
        for (i = 0; i < 15; i = i+1)
        begin 
           .....
        VectorY_next = count[11:8] >> 4 - 4'd7;
        completed = (count == 4'd16 * (8'd256 + 1));
    end
endmodule

And probably do the same for other ports too.To run using systemverilog, just use -sv option in the command line.

Net 'VectorY[0]', or a directly connected net, is driven by more than one source, and at least one source is a constant net. (ELAB-368)

1 Answers1