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I am running a testbench using systemverilog over OVM using vcs. I want to save my simulation after some reset phase and then return to it later on in the test, or/and from another testbench. Is this possible using systemverilog cmds?

Alternatively is there a way to do this using vcs cmds? Thanks

ronenmiller
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1 Answers1

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Yes there is $save command in vcs, to save the session. That command needs to be placed in the design itself.

In your case you can do something like this. 

initial
begin
      reset = 1'b1; // Asserting Reset
  #10 reset = 1'b0; // Deasserting Reset
      $save ("reset_state.chk");
  //  Post reset data
end

This will save the reset state in reset_state.chk file.

Karan Shah
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  • So how would I do that from a systemverilog class (OVM sequence). Or do I have to use initial begin? – ronenmiller Oct 20 '16 at 08:41
  • Yes one way is to use $save in program/module. To use save restore mechanism from class, I believe, you may need to refer the VCS user guide. – Karan Shah Oct 20 '16 at 10:38