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I have an accelerator attached to my RISC V core and until now I was sending data through the RoCC interface. Now I want to send and receive the data through the L1 cache. I know mem field connects to the cache but how exactly do we perform load and store operations through the L1 cache.

CV_Ruddha
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    Check out the AccumulatorExampleModuleImp in RocketChip. It's rather simple but does use the L1 cache interface to perform loads. https://github.com/chipsalliance/rocket-chip/blob/77b4e6b84c91aa0617c7e54c7c57c8783bcd30b3/src/main/scala/tile/LazyRoCC.scala#L125 – Jack Koenig Nov 14 '19 at 02:18
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    Hey Jack, thanks for responding, I understand how I can perform store but in the AccumulatorExampleModuleImp, for load we have the address and the tag but where exactly are we getting the data from? Cos the io.mem.req.bits.data is set to zero. – CV_Ruddha Nov 14 '19 at 20:27
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    The load data comes back in the response `io.mem.resp`, you can see the loaded data used here: https://github.com/chipsalliance/rocket-chip/blob/77b4e6b84c91aa0617c7e54c7c57c8783bcd30b3/src/main/scala/tile/LazyRoCC.scala#L148 – Jack Koenig Nov 15 '19 at 01:19
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    Thanks, exactly what I was looking for. – CV_Ruddha Nov 15 '19 at 01:52
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    It can't accept a transaction every cycle. The `req` interface is a `ready-valid` interface so you should only count your request as received if `mem.req.fire()`is true (ie. `io.req.ready && io.req.valid`). – Jack Koenig Nov 19 '19 at 06:48
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    Also, how does the io.mem.req.ready signal get asserted? What is the stimulus here? Since whenever I assert a bool(true) or bool(false) I get an error saying male is being used as a female and vice versa. – CV_Ruddha Nov 19 '19 at 21:37
  • `ready` and `valid` on a ready-valid interface go in opposite directions. As the requestor, you specify when the request is "valid", but it is the receiver's responsibility to determine when they are "ready" to receive your request. Basically, the other side of the interface is driving `ready`, and you can only consider the request accepted when both `valid` (driven by you), and `ready` (driven by them) are asserted in the same cycle. – Jack Koenig Nov 19 '19 at 21:54

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