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I've implemented 32 bit rocket chip with rocc example, but in accumulator example while accessing data through hella cache interface using do_load instruction. The io_mem_response_valid signal remains high for two clock cycle so data in reg file is overwritten by data of next memory location. vivado simulation waveform for simple do_load instruction

May be memory response interface default setting to transfer 64 byte or else. please assist me. how to change burst size?

Thanks & Regards, Sanket

Sanket Khandare
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  • Seems like somehow you are confusing cache line fill with register write. What happens if the program does a byte read to an odd address? – Erik Eidt Jan 14 '20 at 10:13
  • Thanks for reply i managed to solve the issue, There is io.mem.req.bits.size we need to send io.mem.req.bits.size := log2Ceil(4).U (i.e. 2) for accepting 32 bits over mem response interface. I went through older berkely's lab documentation for coproccesor, There is typ signal for same interface; but there is no typ signal anymore. May be it replaced with size signal. – Sanket Khandare Jan 15 '20 at 11:23

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I just changed value of io.mem.req.bits.size = log2Ceil(4).U (i.e. 2) from https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/LazyRoCC.scala. which may informed response size for io.mem.resp interface.

Sanket Khandare
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