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I need only 32-bit instructions but gcc compile my c code with compressing. I tried -march= options without c but compressed instructions still remain. How can I get uncompressed(?) instructions?

MuzaffarShaikh
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SweetCaffe
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  • As far as I can see, GCC hasn't an option to pessimize code that way. Why do you think this is desirable? – Armali Nov 18 '21 at 19:03
  • In my simple riscv core, core reads only 32-bit instructions. If there is 16-bit instructions , core reads concatenated instructions (16-bit instruction + 16-bit instruction ). – SweetCaffe Nov 19 '21 at 06:41
  • That does not explain to me why you don't want that. Surely the _core_ is able to correctly recognize two 16-bit instructions even if read at once, don't you think so? – Armali Nov 19 '21 at 08:01
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    @Armali No, some RISC-V cores (in particular, FPGA softcores) don’t support 16-bit instructions at all, that’s why the “standard extension for compressed instructions”, aka “extension C”, is an *extension*. The 16-bit instructions fit into holes in the 32-bit encoding, so the code won’t be misinterpreted, but on an unsupported implementation it’ll just take an invalid operation exception. – Alex Shpilkin Dec 09 '21 at 15:05

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Per the GCC manual section on RISC-V command-line options, you can pass a standard RISC-V ISA subset name as specified in Vol. 1 Ch. 27 of the manual (PDF, source) in -march=. For example, to compile for base 32-bit RISC-V with no extensions at all, add -march=rv32i to your compiler flags.

Alex Shpilkin
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