is my RISC V interrupt control flow understanding correct？

Question

I'm kinda confused with the syscall code and mcause code. I want to implement a software interrupt on a rv5 cpu with ecall instruction, and the control flow (to my understanding) is :

a7<-system call number
ecall{
  mcause<-11
  pc<-interrupt_handler
}
interrupthandler(mcause,a7){
switch(mcause):
case 0
case 1
...
case 11:switch(a7)  //syscalls
                 case 0:
                 case 1:
                 case 2:
                 case 3:
}

I just want to make sure the part involving mcause code and syscall code are understood correctly,so some other control flows and omitted(like mepc)