verification using Questasim

Question

I am trying to verify my design in Questasim and the design is in VHDL. I am using Makefile. The command is

vcom -93 -work $(work) $(RTL) $(SVTB1) $(SVTB)

It is invoking VHDL compiler, but it is not displaying the master_driver signals.
Can anybody tell the solution?

You would need to post the entire makefile for us to know what is wrong — noobuntu, Aug 23 '17 at 14:51
comp0: vlog -work $(work) $(RTL) $(INC) $(SVTB1) $(SVTB) comp1: vcom -93 -mixedsvvh -work $(work) $(RTL) $(SVTB1) $(SVTB) — Tsr, Aug 24 '17 at 08:54
@noobuntu is there any command for compiling VHDL as well as SV files together? — Tsr, Aug 29 '17 at 11:12

score 0 · Answer 1 · answered Aug 30 '17 at 05:11

0

I got one solution but I don't know whether it's a perfect one. The solution to my question is that divide SV and VHDL codes in two different folders and compile them separately. But the work folder should be same.

answered Aug 30 '17 at 05:11

Tsr

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verification using Questasim

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