VHDL Reading text from files, then storing and comparing them to create a Test Bench

Question

I have a text file representing adc values in the integer format from a circuit, which looks like,

0000
0001
0005
3864
2290
1234
.
.
.
0002
0004
0006
4532
3457
.
.
.

the first 3 integers always represent a header and the subsequent 256 integer values comprise of one block. I have written a VHDL code (algorithm) to analyze this file which stores the several characteristics of this file. I have also written a testbench which reads the file and sends each value in one row to the analyzer code. The values are currently sent one by one to the analyzer component as described in my testbench code here.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use std.textio.all;



entity HFA_tb is
end HFA_tb;

architecture behave of HFA_tb is

--clock 100 MHz change to any value suitable
constant c_CLOCK_PERIOD : time:= 100 ns;
signal r_CLOCK      : std_logic  := '0';
--**signal r_ENABLE     : std_logic  := '0';
signal r_adcpulse   : integer; 
signal r_hitstart   : integer;   ---output of single threshold
signal r_hitend     : integer;
signal r_hitpeak    : integer;
signal r_peaktime   : integer;
signal r_hitsum     : integer;
signal r_opready    : std_logic := '0';





--more signal

--describe HFA component here (Unit Under Test)

component HFA is
 port (
   adcpulse_i     : in integer;
   clk          : in std_logic;
   hitstart_o   : out integer;   ---output of single threshold
   hitend_o     : out integer;
   hitpeak_o    : out integer;
   peaktime_o   : out integer;
   hitsum_o     : out integer;
   opready_o    : out std_logic

   );
 end component HFA;

begin

  --Instatiate the unit under test
  UUT : HFA
  port map (
    clk         => r_CLOCK,
    adcpulse_i    => r_adcpulse,
    hitstart_o  => r_hitstart,
    hitend_o    => r_hitend,
    hitpeak_o   => r_hitpeak,
    peaktime_o  => r_peaktime,
    hitsum_o    => r_hitsum,
    opready_o   => r_opready
  );

 p_CLK_GEN : process is
  begin
   wait for c_CLOCK_PERIOD/2;
   r_CLOCK <= not r_CLOCK;
 end process p_CLK_GEN;


  --main testing logic for reading from text file; feed in the loop and     check output

  process
   file in_buffer       :   text;
   file out_buffer      :   text;
   variable v_ILINE     :   line;
   variable v_OLINE     :   line;
   variable v_adcValue  :   integer;

  begin

    file_open(in_buffer,"test.txt",read_mode);

    file_open(out_buffer,"results.txt",write_mode);


    while not endfile(in_buffer) loop
      readline(in_buffer, v_ILINE);
      read(v_ILINE, v_adcValue);

      r_adcpulse <= v_adcValue;

      wait for c_CLOCK_PERIOD;

  end loop;

   if endfile(in_buffer) then

     write(v_OLINE, string'("hit_start_time"));
     writeline(out_buffer, v_OLINE);

     write(v_OLINE, r_hitstart);
     writeline(out_buffer, v_OLINE);

   end if;

  wait for c_CLOCK_PERIOD;

    file_close(in_buffer);

    file_close(out_buffer);

   wait;

  end process;  


 end behave; 

As you can see from my example the current testbench is only capable of reading one line at a time and sending it to the analyzer. What I want it to do, is to strip the header(first 3 integers) store it, and again join it to the text file when it is done processing one block of 256 integers? any hints will be much useful in this direction. My approach is based on data word comparators, data word description