assign statement in Questa Sim yields x as output

Question

I wrote a module that should "or" a signal with a delayed version of itself. But, when I simulate my design, the output always goes x instead of 1. I have no idea why. Here is how I wrote my design:

module DUT(
input data_in,
input dw,
input rst,
output error
);
wire Edge;
wire #4 delayed_data_in;

assign Edge = data_in ^ delayed_data_in;
assign delayed_data_in = data_in;
always@(dw,Edge,rst) //Latch 1
begin
    if(rst)
    begin
        error <= 0;
    end
    else if(dw)
    begin
        error  <= Edge;
    end
end
endmodule

The delayed version behaves as expected, but Edge and error just go to "x" instead of 1.

Answer 1

I get a compile error with your code. You can try to compile your code on different simulators on edaplayground. The problem is that you can not make a procedural assignment to a net (error). To fix the error, change:

output error

to:

output reg error

With this simple testbench, the x's are resolved:

module tb;

    reg data_in;
    reg dw;
    reg rst;
    wire error;

DUT dut (
        // Inputs:
    .data_in  (data_in),
    .dw       (dw),
    .rst      (rst),
        // Outputs:
    .error    (error)
);

initial begin
    data_in = 0;
    dw = 0;
    rst = 1;
    #30 rst = 0;
    #50 $finish;
end

endmodule