I'm trying to write a makefile for compiling and simulating some vhdl code.
Is there a way to create a project from linux/windows command line ?
It is straightforward if you open the tool and run "project new" but there's no documentation for doing it from the command line.
I don't know how to use the project command directly from command line. But I've another method to do it. If you are into command line, you might know it already.
Anyway, you can write a .do file which contains the project commands then use vsim -c -do filename.do to execute it.
for example, my filename.do contains "project new . pro_name"
My recommendation would be not to use projects, they will get in the way.
As Rakend already mentioned just use .do files which are simple and you have a full Tcl interpreter to your disposal if you want to do some extra stuff.
If you want to use makefiles then compile your code manually and then run vmake to create the Makefile for you. However, vcom/vlog are quick so .do is all you need.
Good luck,
Hans.
