Verilog HDL syntax error near text “for”; expecting “endmodule”

Question

 module alu(input logic [31:0] a, b,
              input logic [2:0] f,
             output logic [31:0] y,
             output logic zero);  

    wire [31:0] ANDed, ORed, SLT, sum, cout, bn;
    wire set_less;
    reg zero_detect;
    genvar i;

    //This segment will take 2s complement of B
    for(i = 0; i < 32; i = i+1) begin
     assign bn[i] = b[i] ^ f[2];
    end

    //This segment will compute the 32-bit addition
    assign sum[0] = (a[0] ^ bn[0]) ^ f[2];
    assign cout[0] =(a[0] & bn[0]) | ((a[0] ^ bn[0]) & f[2]);

    for(i = 1; i < 32; i = i +1) begin
     assign sum[i] = (a[i] ^ bn[i]) ^ cout[i-1];
     assign cout[i] = (a[i] & bn[i]) | ((a[i] ^ bn[i]) & cout[i-1]);
    end

    //This segment will complete the AND operation
    assign ANDed = a & bn;

    //This segment will complete the OR operation
    assign ORed = a | bn;

    //set less than, A < B then the first digit of the sum will be 1
    assign set_less = sum[31];
    assign SLT = {{31'b0000000000000000000000000000000}, set_less};

    //Set the zero flag if there aren't any 1's in the output
    assign zero = !(|y);

    //select the output based on the function input
    assign y = f[1] ? (f[0] ? SLT : sum )
                         : (f[0] ? ORed : ANDed);
    endmodule

Error (10170): Verilog HDL syntax error at alu.sv(15) near text: "for"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword.

Error (10170): Verilog HDL syntax error at alu.sv(23) near text: "for"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword.

Error (10170): Verilog HDL syntax error at alu.sv(26) near text: "end"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword.

Error (10112): Ignored design unit "alu" at alu.sv(4) due to previous errors

I see nothing wrong with your syntax. perhaps there is a problem with the code that comes before the module — dave_59, Mar 13 '18 at 06:29
the question is which tool and which version of the tool you are using. It might not support 'for' loops without `generate..endgeneerate` around `for` loops in your case. — Serge, Mar 13 '18 at 14:18
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ LITE EDITION — Eddy Mejia, Mar 13 '18 at 23:14
ModelSim - INTEL FPGA STARTER EDITION 10.5b Revision: 2016.10 Date: Oct 5 2016 — Eddy Mejia, Mar 13 '18 at 23:14

score -1 · Answer 1 · answered Mar 13 '18 at 11:19

-1

genvar variable should only be used with generate block. Use for loop within generate-endgenerate block to get rid of errors.

answered Mar 13 '18 at 11:19

Vinayak Hiremath

1
2

Sorry. That is not true. In Verilog 2005 if was permitted to use a _genvar_ without a _generate_ statement. – Matthew Taylor Mar 13 '18 at 11:57
@MatthewTaylor are you sure? as far as i know, this is true for 'system verilog' 2012 – Serge Mar 13 '18 at 12:27
Yes. I teach Verilog. There's a slide about this on the Verilog course I teach. – Matthew Taylor Mar 13 '18 at 13:59
@MatthewTaylor thanks, you were correct, i found it. – Serge Mar 13 '18 at 14:18
@vinayak See https://stackoverflow.com/a/25924620/2755607, and I suggest deleting this answer – dave_59 Mar 13 '18 at 15:02
So how would I go about fixing it? – Eddy Mejia Mar 13 '18 at 23:12

Verilog HDL syntax error near text “for”; expecting “endmodule”

1 Answers1