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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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Decoding pcie config space capabilites manually - looking for example

I don't have an o/s running so I can't decode pcie using something like lspci (I wish lspci would take input from a file!). I have a hex dump below (this is a Xilinx Ultrascale FPGA but the question is generic), I'm trying to understand where the…
TomKeddie
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Does accessing mapped pinned host (or a peer device) memory require GPU copy engine?

Assume the GPU has one execution engine and one copy engine. When inside a CUDA kernel the threads access the host memory, does it make the copy engine busy? Does it consequently block all asynchronous memory copy operations to/from the device in…
Farzad
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Linux PCI Driver calls init, but not probe

I'm developing a driver for an FPGA-board connected to my machine via an PCIe expansion slot, and everything works great if the board is powered on prior to the PC. However, if I book up my computer first and then the FPGA board, I get the rather…
Yeraze
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BAR regions unallocated after PCIe rescan on Linux

I have an FPGA card attached to PCIe on a Linux system. I can re-program the FPGA and then echo 1 > /sys/bus/pci/rescan and my card shows up in lspci. However the BAR regions aren't allocated any memory: Region 0: Memory at (64-bit,…
user3767592
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Using pci_enable_msi_block

I am trying to enable multiple MSI irq lines in a kernel module. I am operating in RC mode. The problem is when I call pci_enable_msi_block() it will not allocate more than 1 MSI. If I call pci_enable_msi_block(dev, 32) it will return 4 (which I…
whh4000
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How to map a PCIe area with VxWorks?

This is my first post :) I am using VxWorks 6.9 and an Intel Sandy Bridge board. I would like to know how to map a PCIe memory area in my application. The PCIe memory area is a part of the Graphic memory and it's physical address is 0x80000000. I’m…
user3407317
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How does GPUDirect enforce isolation on a shared device

I have been reading here https://developer.nvidia.com/gpudirect about GPUDirect, In there example there is a network card attached to the PCIe together with two GPU's and a CPU. How is isolation enforced between all clients trying to access the…
yonigo
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Can I use I/O ports (asm: `in, out`) to transfer data via PCI Express on modern x86_64 CPU?

Can I use I/O ports (asm: in, out instructions) to transfer data via PCI Express on modern x86_64 CPU or I can uses only BARs for MMIO(Memory Mapped I/O) and for DMA(Direct Memory Acces to memory mapped regions of PCI-E devices)?
Alex
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Sending the same data to N GPUs

I have 4 GPUs hung off the same PCIe switch (PLX PEX 8747) on a Haswell based system. I want to send the same data to each GPU. Is it possible for the PCIe switch to replicate the data to N targets, rather than do N separate transfers? In effect is…
ShaneCook
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CUDA - transferring a buffer to multiple devices

If I have three gpus and I need to transfer a huge buffer to all three of them, will it make any difference if I use a CUDA stream for each one of them so that their copy engines can perform the transfers simultaneously? I mean: the PCI-E bus to…
Marco A.
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IoGetDevicePropertyData() returns STATUS_OBJECT_NAME_NOT_FOUND

I'm updating a functioning KMDF driver for a PCI device, using WinDDK 7600.16385.1 and OSR's ddkbuild.cmd, targeting WLH, testing on Win7 x86 and x64. I'm attempting to retrieve the DEVPKEY_Device_LocationPaths property. The Device Manager Device…
dr-stevep
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WMI: PCIExpress

Does anybody know the way to get devices attached to PCI Express slots by using WMI? I've been using Win32_PnPEntity class, but I can't make a distinguish between PCI and PCI Express devices.
d3rzKy
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Linux How to test a PCIe driver?

I wrote a simple PCIe driver and I want to test if it works. For example, If it is possible to write and read to the memory which is used from the device as well. How can I do that? And which stuff should be proved too?
Peter
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How do I inform a user space application that the driver has received an interrupt in linux?

I have a PCIe device that will send a hardware interrupt when a data buffer is ready to be read. I believe the best approach for this is to use signals but I'm not entirely sure how. What I believe I need to do is: Save the PID of the user space…
Chris
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Address assignment on a 64 bit linux host to a 64 bit pcie card

I am using a 64 bit PCI express card on a 64 bit linux host, problem is that it's bars are 64 bit but always get an address that lies in 32 bit address range i.e. higher 32 bit of BAR is always zero. How can I enforce it to use real 64 bit addresses…
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