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As known, Power8 supports Coherent Accelerator Processor Interface (CAPI): https://www.nextplatform.com/2015/06/22/the-secret-of-power8-capi-is-addressing/

Hardware Managed Cache Coherence

  • Enables the accelerator to participate in “Locks” as a normal thread Lowers Latency over IO communication model

https://www.microway.com/download/presentation/IBM_POWER8_CPU_Architecture.pdf enter image description here

What does it mean “Locks”? Does it mean, that we can use spin-lock to protect shared-memory for safe access to it using it from CPU-Cores and PCIe-devices (ASIC, FPGA, ...)?

I.e. does it mean, that we can use spin-lock, atomic-operations, even LL/SC-atomic operations across PCI Express bus?

Alex
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    Take a look [at the whitepaper](https://www-304.ibm.com/webapp/set2/sas/f/capi/CAPI_POWER8.pdf) from IBM: "*Fundamentally, the rich set of commands that the accelerator can send to the PSL reflects all of the types of memory accesses available to the POWER8 cores themselves (such as reads, reads with intent-to-modify, reservations, locks, writes, and writes to highest point of coherency)*" – Margaret Bloom Jun 10 '17 at 12:46
  • @Margaret Bloom Thank you! It seems that this is answer. I.e. PCIe allows to use any atomic operations, including composite atomic operations LL/SC (reservations), therefore can be implemented spin-lock across PCIe (external-FPGA <--> CPU), page 6. But in this case is guaranteed only the possibility of atomic access to CPU-memory/cache from the FPGA, and only if FPGA contains PSL (power service layer) and if CPU Power8 contains CAPP (coherent accelerator processor proxy). And both CAPP+PSL = CAPI (Coherent Accelerator Processor Interface). – Alex Jun 10 '17 at 13:47

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So P8 doesn't support the PCIe atomics as defined by the PCIe sig (optional feature of PCIe).

It does support some proprietary atomic primitives that are used by CAPI. I don't know if it's possible to exploit them from a non-CAPI adapter on P8.

Benjamin Herrenschmidt
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  • Thank you! I.e. is it unknown whether the CAPI uses compound atomic operations supported by PCI sig, or the CAPI implements its own protocol for compound atomic operations over the PCIe, by using CAPP on CPU and PLS on device? – Alex Jun 12 '17 at 23:02