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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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pci_Driver.probe not being called

I'm getting started in Linux Device Driver development for a PCI device connected via a laptop's PCIe expansion slot. On boot, everything works beautifully. However, I'm trying to get basic Hotplug support online. When I eject the card, I can see…
Yeraze
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In Infiniband, what mapping in PCIe-BAR, the internal buffer of Infiniband card or the remote computer's RAM?

As we know, Infiniband allows RDMA - direct access to the memory of the remote computer. It is also known, that the PCI-Express (endpoint) devices, including the PCIe-card Infiniband, are able to communicate in two ways: IO Ports (in / out)…
Alex
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Peer-to-Peer CUDA transfers

I heard about peer-to-peer memory transfers and read something about it but could not really understand how much fast this is compared to standard PCI-E bus transfers. I have a CUDA application which uses more than one gpu and I might be interested…
Marco A.
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DMA from Linux kernel-space to PCIe card

I am trying to write a linux driver for a PCIe device - the Adlink PCIe 7300A High-Speed digital-IO card. The driver works fine for normal memory transfer, but attempting to use the card's bus-mastering capabilities to initiate DMA transfer of a…
s.brookes
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Can a PCIe endpoint access Root Complex BARs?

I am working on an embedded PCIe system where two SoCs are connected together, the Host is a Root Complex, the Slave is an Endpoint. The Host will run Linux. Typically the Host SoC provides memory windows, where the Endpoint BARs are mapped. This…
user2504336
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PCI Express validation using driver

I'm using Windriver Jungo for testing PCI express device connected to my PC. I can able to read/write memory in 8/16/32/64 bit modes and the board responding very well. But my doubt is that, according to PCI express specification we can send a TLP…
Premjith
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PCIE endpoint to endpoint transaction

I would like to clarify that the endpoint to endpoint transactions (peer to peer transaction) of two PCIE endpoints behind a PCIE switch are not forwarded to the root complex. I googled around and understand that if the transaction from Endpoint #1…
Dien Nguyen
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Linux block driver merge bio's

I have a block device driver which is working, after a fashion. It is for a PCIe device, and I am handling the bios directly with a make_request_fn rather than use a request queue, as the device has no seek time. However, it still has transaction…
Inductiveload
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Booting from PCIE USB 3.0 Expansion Card

I just bought a PCIE Expansion Card for USB 3.0 support. It works pretty well inside Windows. However, I did not managed to get my USB 3.0 thumbdrive booted-up (which is connected to the expansion card) as there is no option to choose from the boot…
harrisong
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PCIE DriverKit cannot be loaded correctly due to entitlements issues

My question I already have the correct entitlements, provisioning profile and development certification, and I have turned off SIP, turned on systemextensions developer on, but it still shows provider entitlements check failed. Similar…
xmx
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macOS DriverKit: Making PCI dext to replace built-in driver

I'm trying to write a user-space PCI driver in DriverKit for educational/research purposes. I've found an example from WorthDoingBadly which has the boilerplate code for a PCI device dext (I've removed the exploit code). I've modified it to match a…
Mads Y
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Documentation on MSI Address/Data register content expectations for AMD cpus?

Where I can find info on AMD Ryzen CPUs and how they expect MSI address/data to be programmed? The Intel manual is crystal clear in its description (pictured below) but MSI Address/Data registers are implementation dependent according to the PCIe…
Omar Darwish
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How to tell linux retrain and scan PCIe bus?

We have an embedded board that has an iMX8M-Plus Processor and Linux v5.4.161. This board has one PCIe bus and that one is connected to an FPGA. When we power up the board, the FPGA is not yet configured, so it acts as if it was not on the PCIe…
Mehmet Fide
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SR-IOV - Difference between PF and VF

I am looking into SR-IOV and am looking for certain examples that what are exactly the things that a PF can do that a VF cannot. For example one thing is that a VF can not create further VF. There is a mention: A PCI Function that supports the…
Ameer Usman
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Writing to persistent memory in PCIe

I want to read and write to a persistant memory(for testing now ddr is connected) in my PCIe device (FPGA) on an Intel Linux system. The memory is exposed in a particular bar (say bar 2). How to access this persistant memory. I looked into examples…
Rahul K V
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