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Questions tagged [persistent-memory]

Use this tag for questions related to programming for persistent memory (also known as SCM or NVRAM), which is a type of byte-addressable non-volatile memory that is physically present on the main memory bus and can be accessed using regular load and store instructions. Do not use this tag for hardware related and/or end-user issues, those might fit on Super User.

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Why does CLFLUSH exist in x86?

I recently learned about the row hammer attack. In order to perform this attack the programmer needs to flush the complete cache hierarchy of a CPU for a specific number of addresses. My question is: why is CLFLUSH necessary in x86? What are the…
Martijn
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Intel's CLWB instruction invalidating cache lines

I am trying to find configuration or memory access pattern for Intel's clwb instruction that would not invalidate cache line. I am testing on Intel Xeon Gold 5218 processor with NVDIMMs. Linux version is 5.4.0-3-amd64. I tried using Device−DAX mode…
Ana Khorguani
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(Persistence) ordering of Intel non-temporal stores to the same cache line

Do non-temporal stores (such as movnti), to the same cache line, issued by the same thread, reach the memory in program order? So that for a system with NVRAM (like Intel Cascade Lake processor with an Intel 3D XPoint NVRAM), in case of a crash, the…
galym
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On x86-64, is the “movnti” or "movntdq" instruction atomic when system crash?

When using persistent memory like Intel optane DCPMM, is it possible to see partial result after reboot if system crash(power outage) in execution of movnt instruction? For: 4 or 8 byte movnti which x86 guarantees atomic for other purposes? 16-byte…
dangzzz
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Is clflush or clflushopt atomic when system crash？

Commonly, cacheline is 64B but atomicity of non-volatile memory is 8B. For example: x[1]=100; x[2]=100; clflush(x); x is cacheline aligned, and is initially set to 0. System crashs in clflush(); Is it possible x[1]=0, x[2]=100 after reboot？
dangzzz
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How does DC PMM (memory mode) cache coherence behave?

Current setup: Most recent intel architectures today have non-inclusive L3 cache where each slice (+CHA) includes a "snoop filter" that contains the location information an L3 directory would have provided if it were inclusive (This design choice is…
BrewM4ster
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Counting number of allocations into the Write Pending Queue - unexpected low result on NV memory

I am trying to use some of the uncore hardware counters, such as: skx_unc_imc0-5::UNC_M_WPQ_INSERTS. It's supposed to count the number of allocations into the Write Pending Queue. The machine has 2 Intel Xeon Gold 5218 CPUs with cascade lake…
Ana Khorguani
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How to read stale values on x86

My goal is to read in stale and outdated values of memory without cache-coherence. I have attempted to use prefetchnta to perform a non-temporal load, but it failed to fetch outdated values. I am looking into performing some kind of Streaming…
Louis Jenkins
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Why “movnti” followed by an “sfence” guarantees persistent ordering？

SFENCE prevents NT stores from committing from the store buffer ahead of SFENCE itself. NT store data enters an LFB directly from the store buffer. Therefore SFENCE can only guarantees the ordering of data entering LFB. For…
dangzzz
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Does clwb take care of the write in store buffer?

Intel software manual says clwb "Writes back to memory the cache line (if modified) that contains the linear address specified with the memory operand from any level of the cache hierarchy in the cache coherence domain. The line may be retained in…
Arun Kp
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Writing to persistent memory in PCIe

I want to read and write to a persistant memory(for testing now ddr is connected) in my PCIe device (FPGA) on an Intel Linux system. The memory is exposed in a particular bar (say bar 2). How to access this persistant memory. I looked into examples…
Rahul K V
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Do I need to externally call flush if using cuda api to copy from GPU Memory to Persistent Memory?

I am using Cuda API: cudaMemcpyAsync ( void* dst, const void* src, size_t count, cudaMemcpyKind kind, cudaStream_t stream = 0 ) to copy data from GPU memory from CPU memory. In case copying the data from CPU memory to Persistent Memory using…
Ashikee AbHi
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How does Linux handle Intel's Optane Persistent Memory Modules under Memory Mode?

I was wondering whether the Linux kernel did anything special or performed any optimizations when the underlying system employs Persistent Memory Modules in Memory Mode (Near-Memory DRAM cache and NVRAM as main memory). I've tried looking in…
Louis Jenkins
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RISC-V instruction to write dirty cache line to next level of cache

Are there any RISC-V instructions to write-back dirty cache line to next level of cache, or to main memory, like clwb in x86 or cvac in ARMv8-A? I want to ensure commit to non-volatile persistent memory. My intention is to adapt ARMv8_A code…
Arun Kp
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Distinguishing volatile vs persistent variable, does it affect correctness?

From my understanding of persistent programming models, it is up to the programmer to correctly distinguish the volatile variables as opposed to the persistent variables. Persistent variables would require some kind of atomic updates so that if a…
yjsoh
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