Stack Overflow
Stack Overflow

Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

449 questions
3
votes
1 answer

Are writes on the PCIe bus atomic?

I am a newbie to PCIe, so this might be a dumb question. This seems like fairly basic information to ask about PCIe interfaces, but I am having trouble finding the answer so I am guessing that I am missing some information which makes the answer…
dykeag
  • 554
  • 3
  • 11
3
votes
1 answer

Where are NVMe commands located inside the PCIe BAR?

According to the NVMe specification, the BAR has tail and head fields for each queue. For example: Submission Queue y Tail Doorbell (SQyTDBL): Start: 1000h + (2y * (4 << CAP.DSTRD)) End: 1003h + (2y * (4 << CAP.DSTRD)) Submission Queue y Head…
tweak
  • 43
  • 7
3
votes
1 answer

Precise details of writing a byte into PCIe address space from CPU

I am extremely confused about the exact series of steps involved in having the CPU write a value into a PCIe card's memory. It's very difficult to understand the precise meaning of stuff you read on the internet, so I'm hoping someone can read my…
Marco Merlini
  • 875
  • 7
  • 29
3
votes
0 answers

How to get details of PCI device enumeration when Windows starts up

We made a motherboard. A PCIe switch (1 upstream port, 4 downstream ports) is used. Each downstream port directly leads to a PCIe slot. There is a problem that has been plagued for a long time. The No. 2 slot does not recognize the device and has…
lizzoe
  • 51
  • 3
3
votes
1 answer

What are the most common busmaster operations, and how are they better than regular DMA?

Can someone list the most common operations that use the bus mastering provision of the host bus? I can list a few.. 1) The GPU transfers the overall framebuffer to the video card using bus-mastering over PCI-e (in recent x86). 2) The ethernet card…
user2277550
  • 553
  • 7
  • 22
3
votes
1 answer

Mapping MMIO region write-back does not work

I want all read & write requests to a PCIe device to be cached by CPU caches. However, it does not work as I expected. These are my assumptions on write-back MMIO regions. Writes to the PCIe device happen only on cache write-back. The size of TLP…
Taekyung Heo
  • 51
  • 1
  • 6
3
votes
0 answers

Is it normal that the strange src addr appears when DMA(PLX PEX 8733) runs a while?

I am curious about the processing of DMA(PEX 8733) driver transfer, and using kzalloc to get a piece of buff for observing a running DMA descriptor table. It is according to DMA spec, the descriptor format is like: descriptor format When I start my…
Nick Lin
  • 31
  • 3
3
votes
1 answer

Why there are 6 Base Address Registers (BARs) in PCIe endpoint?

After some reading about the PCIe, I came around the PCI compatible configuration headers and after understanding the header there is Base address Register(BAR) field. Where there are total 6 BARs in each PCIe endpoint. Why there are 6 BARs and not…
Rahul Talole
  • 137
  • 1
  • 2
  • 9
3
votes
1 answer

How do PCIe devices advertise multiple virtual functions to Linux?

SR-IOV lets PCIe devices expose a single physical function and multiple virtual functions. How does the kernel detect that a device supports virtual functions? Is it a part of the PCIe configuration registers? Where in the kernel are devices tested…
Patrick Collins
  • 10,306
  • 5
  • 30
  • 69
3
votes
2 answers

What is the equivalent of 'Cache line size' in PCIE?

In PCI configuration space, Cache line size indicates system cacheline size in units of DWORDs. This register must be implemented by master devices that can generate the Memory Write and Invalidate command. The value in this register is also used…
BasavarajaMS
  • 161
  • 3
  • 13
3
votes
1 answer

Can we use x86_64 CPU atomics to generate on PCI Express the compound atomic operations?

As you know, starting with version 2.0, PCI Express supports compound atomic operations: FetchAdd, Swap, CAS: https://pcisig.com/sites/default/files/specification_documents/ECN_Atomic_Ops_080417.pdf Also known, that x86_64 CPU has assembler…
Alex
  • 12,578
  • 15
  • 99
  • 195
3
votes
1 answer

PCI nodes in Device Tree

Is it necessary that the nodes shown in "lspci" output, have to be defined in device tree ? I have device tree file for P2041RDB. In that only one node is created for pci i.e. bus 0. Now I have customized the reference board and connected one…
Savan
  • 78
  • 1
  • 11
3
votes
0 answers

Linux: accessing PCIe status registers

I need to count the number of PCIe correctable and uncorrectable errors detected in Linux. How and where do I start? Is a Linux device driver an appropriate approach to count such errors? If a driver is appropriate, then what type of driver? …
tartartar
  • 41
  • 2
3
votes
2 answers

PCIe - DMA: Consistent vs. Streaming Memory

Currently I'm adding DMA to my PCIe driver for Linux. As I'm reading through the documentation it makes mention of consistent, or coherent, memory by using the API: pci_set_consistent_dma_mask(...) but never really talks about why to use it or what…
user2205930
  • 1,046
  • 12
  • 26
3
votes
0 answers

Is it possible to execute-in-place from a memory mapped pcie device?

In the linux kernel I know that it's possible to memory map in pcie memory. Is it possible to execute from the memory mapped pcie device if it provides a region of memory? For example, I have a PCIe card with an FPGA and some memory on it. I would…
Jay Hirata
  • 71
  • 2
1 2 3
…
29 30