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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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use atomic operations on the PCIe host/device shared memory?

Some PCIe devices (for example FPGA card) can expose segments of its physical memory via host's BARs and the host can access the memory region via the memory devices (on Linux, we can memory mapped the devices to virtual memory). I suppose the…
SCLaker
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How to read /dev/mem using read()

I am trying to read some physical address that is mapped to PCIe device using /dev/mem. The PCIe device is mapped to 0x387ffa000000: bash# lspci -s 1a:00.0 -v | grep Memory Memory at 387ffa000000 (64-bit, prefetchable) [size=32M] So I wrote…
so.very.tired
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How DMA and PCIe play together?

in a PCIe configuration, devices have dedicated addresses and they send data in Peer-to-Peer mode to each other - every device can write when it wills and the switches take care to correctly pass data forward. There is no need to have a "bus…
Emerson Fittipaldi
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smbus access in pcie under windows

I'm looking for a way to control smbus line in PCIe slot of my PC. There's some device connected via PCIe in that slot. And I wanna access it via the SMBus line under Windows. But cannot find any API to use for that. Can you suggest me how to do…
Johan Zigner
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Difference Between PCI and PCIe

I have started reading about PCI and PCIe. I came across a point "From a software standpoint, PCI and PCI Express devices are essentially the same. PCIe devices had the same configuration space, BARs, and (usually) support the same PCI INTx…
Ajeesh
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How to turn off "REAL" PCIe power for a GPU device on Linux

I want to turn off "REAL" PCIe power for a GPU device on Linux. I found some home pages, but they could not cut the "REAL" power. I monitored the AC power usage, but all of them could not cut the real power usage. Could you tell me how to turn off…
Kuniyasu Suzaki
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Linux 4.4 PCIe DMA into userspace pages not working - highmem not usable for DMA?

I am updating an older linux driver that transfers data via DMA to userspace pages which are passed down from the application via get_user_pages(). My hardware is a new x86 Xeon based board with 12GB of RAM. The driver gets data from a VME to PCIe…
Thomas S.
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linux mmap access to PCI memory region from user space application

As a first level test of my PCI driver I hoped I could gain access to the pci_iomap region via the /sys/bus/pci/devices/0000:01:00.0/resource0 file from my user application. The man page for mmap, the sample Program I found, and other posts seem to…
Bill Anderson
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Peer-to-peer communications between PCIe devices?

In order to enable p2p communication between NVMe SSDs and other PCIe devices, I wonder if I need to make some modifications to the Linux kernel and the NVMe driver, and something else? And what modifications should I make? I have searched for some…
Mitsui_Yang
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PCIe peer to peer communication

Can two independent devices(endpoints) communicate with each other without Root Complex being involved in PCIe (according to PCIe specification yes but how)? How can one endpoint know address of other endpoint in case of memory and IO…
Ap.padole
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Intel NVMe drive Performance degradation with xfs filesystem with sector size other than 4096

I am working with NVMe card on linux(Ubuntu 14.04). I am finding some performance degradation for Intel NVMe card when formatted with xfs file system with its default sector size(512). or any other sector size less than 4096. In the experiment I …
Christina Jacob
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QEMU msi emulation

I am working on an emulated QEMU device to simulate an FPGA PCIe interface. I am using the lev-pci device as a base template: https://github.com/levex/kernel-qemu-pci/blob/master/qemu/hw/char/lev-pci.c My device uses MSI interrupts to communicate. …
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How do I discover the PCIe bus topology and slot numbers on the board?

For example, when I use multi-GPU system with CUDA C/C++ and GPUDirect 2.0 P2P, and I use nested PCI-Express Switches, as shown on picture, then I must know how many switches between any two GPUs by their PCI Bus ID, to optimize data transfer and…
Alex
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How could I achieve DMA from a PCIe Verilog core?

I have a PCIe generated core / endpoint with the xilinx core generator tool for a spartan6 fpga on a development board which I have modified a bit to enable MSI and send these every couple of seconds. Also, I did a simple C kernel module on my…
v1ctor23
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What are the performance and architectural differences between PCIe and QPI?

PCIe 3.0 x16 and QPI 1.1 (20 lanes) have identical effective bandwidth (16 GB/s). So, I wanted to get a rough picture about the differences between the two. What are the differences between the two in terms of latency and message rate (number of…
Anuj Kalia
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