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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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How to map physical address from /proc/iomem into user space using mmap?

I want to map PCIe Memory mapped config space into the user space. I am trying to use mmap system call to map the MMCONFIG physical address into the user space. I did some search but not able to figure out what to populate in the fd parameter…
Usr1
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Question About The Sequence Of Calls To Request/Free MSI-X Interrupt Resource On FreeBSD

I have some questions about the sequence of calls to request/free MSI-X interrupt resource on FreeBSD. I tried "amd64 FreeBSD 13.1" and "amd64 FreeBSD 13.2". When requesting MSI-X interrupt resource, I tried the following 2 sequences: *Sequence…
JasonZ
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Register-like PCIe framework for FPGAs?

I'm playing around with a Chinese PCI Express dev board which is based on a Xilinx Virtex-6 365T XC6VLX365T FPGA: https://www.aliexpress.com/item/4001072461753.html?gatewayAdapt=glo2fra The demo code which comes with the board uses the RIFFA…
philpem
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How is the 'data' field provided by the device tree (for platform devce case)?

I can't understand how the device tree information is used in a specific driver. This is a code snippet from linux-5.15.68 drivers/pci/controller/dwc/pcie-designware-plat.c. static int dw_plat_pcie_probe(struct platform_device *pdev) { struct…
Chan Kim
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any known issue with ioread64() / iowrite64() on a PCIe bus?

I have a similar issue mentioned here but with a different behavior. We have an FPGA (from Altera) acts as a 32KB memory on a PCIe bus of IMX8M-Plus CPU (ARM Cortex-A53). I wrote a simple driver to access FPGA's memory. As you can see from lspci…
Mehmet Fide
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Which instructions does a CPU use to communicate with PCIe cards?

I want to understand how a CPU works and so I want to know how it communicates with a PCIe card. Which instructions does the CPU use to initialize a PCIe port and than read and write to it? For example OUT or MOV.
zomega
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Find PCI slot form factor from PCI config space

I am working in C++ on Windows and trying to develop a tool that can identify which PCI slots are in use. I can read PCI config space to find the PCI devices that have slots and which of those slots are in use. I also need to know the form factor of…
Richard Johnson
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Device-Tree Issues with ROCKPro64 PCIe Endpoint

I am attempting to configure the PCIe x4 connection on my ROCKPro64 (RK3399 processor) development board to act as a PCIe endpoint device. My goal is to get utilize Linux's PCIe Endpoint Framework test driver in a similar manner as described in this…
Stahlnusse
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How can I determine the generation/codename of AMD gpu in Linux?

I want to detect the AMD gpu deneration in python code. My case is that to run specific application (davinci resolve), it is required to use amdgpu pro drivers for gpu cards before Vega. And amdgpu pro drivers are not required when AMD gpu is Vega…
Ashark
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FPGA PCIe endpoint prevents the host from rebooting

I am working on implementing an FPGA PCIe endpoint to prototype the interface for one project. The FPGA platform I am using is Synopsys HAPS DX7 S6 featuring a Xilinx Virtex-7 980T device. Besides, I am using a Xilinx cable to program the FPGA via…
GeekTao
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How to dynamically modify QP rate limit in ConnectX-6 Infiniband/VPI adapter

I have a ConnectX-6 Infiniband/VPI Adapter. I can setup the hardware rate limit when creating a qp like this: ... ibv_qp_attr.ah_attr.static_rate = 7; // set qp rate limit to 40Gbps ... ibv_modify_qp(qp, &ibv_qp_attr, flags); ... But I cannot…
Dillion Wang
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UEFI secure boot, how (or will) the PCIE device (firmware) are checked?

Recently I'm searching for info about if PCIe devices are involved in the uefi secure boot, and if so, how it is done. From the uefi specification, the main boot sequence is roughly shown below: Platform init --> load EFI image (may also load EFI…
Quin
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QEMU PCIe TLP Emulation

Does QEMU emulate the PCIe Transaction Layer somehow? When I have a virtual Switch like (https://blogs.oracle.com/linux/post/a-study-of-the-linux-kernel-pci-subsystem-with-qemu) am I able to intercept at least the TLP's going over it? Or is the…
Benedict Schlüter
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Strange PTE value in Hygon x86_64 in Linux - reserved bit 47 set

I have a workstation using Hygon C86 7280 CPU, /proc/cpuinfo shows it has 43 physical address bits, and 48 virtual address bit. But when I mmap a BAR of PCI device (via /sys/bus/pci/devices/0000:nn:00.0/resource0), I can only read 0xffffffff from…
wangt13
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DMA driver with PCIe for transferring information from the FPGA to RAM

I would like to write a driver and software that: the software asks for data every twenty seconds ,and the hardware writes data to the DMA buffer and raises an interrupt when it’s done. Unfortunately I have no experience writing drivers,and I can't…
dys
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