2

I'm trying to compile a VHDL design with modelsim on command line. Is there any way to get an automatical compile order according to the design hierarchy?

I didn't find an option in the documentation of vcom. Only link I found is this, where the solution was to write a brute force script. But it's 10 years ago, so maybe there is anything new. It should be like the option -i of ghdl.

I'm using Altera/Intel Modelsim 18.0 on Linux.

Marph
  • 176
  • 4
  • 15
  • ghdl -i (import) imports specified VHDL files into the working library without analysis. ghdl -m *configuration_or_entity_target* (make) analyzes them in the correct order and elaborates the passed design unit name. ghdl also has an internal makefile generator (--gen-makefile) that outputs the text for a makefile, with import ordered dependencies for elaborating a target. ghdl --gen-depends will output file dependency without the complete makefile text. See [Invoking GHDL](https://ghdl.readthedocs.io/en/latest/using/InvokingGHDL.html). –  Jul 22 '18 at 18:31
  • You are right. I confused -i with -m. If there isn't an option to get the dependencies directly via vcom command, I will try to use the workaround with ghdl --gen-depends. – Marph Jul 23 '18 at 07:12
  • Take a look at this [ModelSim Compile Script](https://www.doulos.com/knowhow/tcltk/examples/modelsim/). I didn't try it but it might help – grorel Jul 23 '18 at 08:22

2 Answers2

1

It seems that in recent versions (tested in ModelSim SE-64 2020.4), vcom supports a new -autoorder parameter, which is described as follows:

Source files can be specified in any order. When all source files can be specified on a single command line, compilation proceeds in a scan phase, followed by a refresh phase. To perform the scan phase over multiple compilations, inhibit the refresh phase with -noautoorderrefresh. Then perform the refresh phase with -refresh_marked (and omit -autoorder).

Just by adding the -autoorder parameter, I was able to easily compile a large VHDL project with many dependencies, that previously failed due to wrong compile order.

H-S
  • 11
  • 1
0

VUnit is an open source tool that will that for you. I recommend the following reading

  1. Installation
  2. Compilation (what you're looking for)

Disclaimer: I'm one of the authors

lasplund
  • 1,350
  • 1
  • 8
  • 17
  • Actually I wrote my full testbench in Python (Cocotb), since I need some Python functionality. I'm not sure if VUnit + VHDL testbench can provide the same functionality, but I will take a look. – Marph Jul 23 '18 at 07:23
  • Depends on how you use Python but you can use VUnit integer_array_t to get data in and out of your simulation and then create Python hooks to produce/consume that data. https://www.linkedin.com/pulse/vunit-matlab-integration-lars-asplund/ can serve as inspiration. – lasplund Jul 23 '18 at 10:46
  • It looks well to me. I just don't know when I will have the time to rewrite my testbench and test it. I will let you know. – Marph Jul 23 '18 at 13:27