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I am unable to read from or write to the AD7928 analog to digital converter (ADC) on the DE1-SoC (Rev. F) development board.

I have the datasheets for the board and the ADC. I am using a mix of custom IP and pre-made hardware components. I have implemented the LEDs, push buttons, and 7-segment displays in Qsys along with the ADC. Base addresses and ranges are set for the memory space of each component. I am controlling the hardware with a C program running in Linux on the dev board. Using a virtual address and offset, I can control all the aforementioned components except the ADC.

The datasheet for the ADC shows 8 registers for reading and 2 for writing. The ADC is set up in Qsys to use one channel (channel 0) out the 8 channels available, running at 12.5MHz. The memory range in Qsys shows correctly that there are 32bytes of addressing assigned to the ADC (8 registers at 4 bytes each). Two of the registers share a read and write command.

Here are the pointers I use for writing the Auto Enable command and reading the 12-bit temperature from channel 0 of the ADC:

// Set ADC to automatically update (write to register offset 4)
*(uint32_t *)(h2p_lw_adc_addr + 4) = 1;

// Read channel 0 from the ADC (read from register offset 0)
temp_in = *(uint32_t *)h2p_lw_adc_addr;

I use the same pointer set-up with the other components, which all work.

I looked at the soft-core processor set-up for the ADC and it has a .h file that contains a command to turn the ADC on, but it seems the hard-core processor systems does not have that command.

Is there some other set-up required for the ADC to be able to use it with the HPS (hard-core processor sys)? The ADC datasheet only shows the 8 registers for control and I have tried both the Auto Enable and Begin Conversion modes. The command registers are shown below.

Command registers for ADC

Gordon
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  • Is the AD7928 in your non-cacheable memory region? – stark Jan 05 '17 at 20:06
  • Qsys shows the addresses starting at 0x000_0020 and ending at 0x000_003F. This address range starts right after the push button memory range, so I believe it is in the correct memory region. I am not familiar with the non-cacheable memory region, but I will read up on it. Thanks! Let me know if you have more questions. – Gordon Jan 05 '17 at 20:18
  • Here's a link: http://stackoverflow.com/questions/90204/why-would-a-region-of-memory-be-marked-non-cached – stark Jan 05 '17 at 20:21
  • Thanks, that's good info. The map for the DE1-SoC shows addresses 0x0000_0000 to 0x03FF_FFFF is in SDRAM. So, I assume the ADC is in cached memory with all the other IP components. – Gordon Jan 05 '17 at 20:34
  • Hi Gordon, this post is very old but I gotta ask this because I have the exact same problem. The values I am getting out of the ADC on my DE1-SoC Linux are all 0's. It is as if ADC is not responding at all. Did you resolve your problem? I have more details at https://forums.intel.com/s/question/0D50P00004atBs4SAE/reading-memory-mapped-adc-values-from-hps-running-linux – Giorgi Aptsiauri Feb 08 '20 at 20:06

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