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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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difference between ISA and IS

I have been learning about computer arcitecture. Other parts of what i learned is no problem, but i had a little of question. The question is what the difference between instruction set architecture and instruction set is? If what i understand is…
WooLyung
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What are the corresponding relationship between "microprogram controller"/"hard-wired controller" and "shared CPU bus"/"specific datapath"?

My textbook says that there are two structures of datapath in CPU: shared CPU bus and specific datapath, and two types of cotrollers: hard-wired controller and microprogram controller. I wonder whether RISC、specific datapath and hard-wired…
Fang
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Are additional opcodes in RISC-V instructions important?

RISC-V was designed so that all instructions would be the same length, hence the existence of different types of instruction formats (I-type, R-type, S-type, etc.) R-format follows this pattern - 7 bits funct7, 5 bits rs2, 5 bits rs1, 3 bits funct3,…
Murad Bashirli
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Setting up a Delay Loop in ARM Assembly

I just started learning ARM Assembly for the Cortex M4 architecture. I have the basic concepts understood, such as loops, memory access, and proper use of instructions. I've come across another loop type that I tried implementing, the delay loop. I…
BlueAngel45
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How do functions access locals in stack frames?

I've read that stack frames contain return addresses, function arguments, and local variables for a function. Since functions don't know where their stack frame is in memory at compile time, how do they know the memory address of their local…
Stonks
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arm instructionLoad Register (immediate) Encoding T4 , P/U/W meaning

From: https://developer.arm.com/documentation/ddi0403/latest page 246, Load Register (immediate) Encoding T4, where to find the definition of P/U/W for bit 10/9/8?
PZ30
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RISCV Mem Virtualization: Sv57x4 58-bit VA is longer than 56-bit PA, how to form it?

I'm exploring RISCV Priveleged Spec and got confused with memory virtualization (especially hypervisor part and two-stage addr translation). How can we form Sv57x4 Virtual Address (VA) for G-stage if basic Physical Address (PA) is shorter? Sv57x4…
katzesaal
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Understanding jump address calculation for different bit ISA

I am trying to understand how jump address is calculated. So far with the MIPS instruction structure (32 bit ISA), I was able to understand this. Solution after reading through some materials I got was that: Concatenate the following: Upper 4 bits…
jazz pop
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(x64) Where can I find CPU instructions usage statistics in contemporary programs?

I'm looking for some statistics which would tell me/show how frequently each instruction from x64 instruction set is used overall in modern programs. I have done some google searches, but I can't find any phrase that would give me anything else than…
sh code
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How many bits do instruction sets have in ARM?

When working with ARM, we commonly understand that the data width residing on an address is 8 bits (I hope this assumption is correct). How does the program counter increment? Does the program counter increment by 4 every time? Inferring that the…
CJC
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Instructions with Long (32 and 64 bit) immediate operands in RISC processors

Are operations with large immediate numbers possible in RISC processors, when the size of the immediate operand does not allow to place it in the 32-bit instruction word (standard for RISC architectures). Say we want to store a 32-bit or 64-bit…
JSpruce
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What is the most basic assembler language that is turing complete?

I want to try and convert a simple language Lox (https://craftinginterpreters.com/the-lox-language.html) to basic assembly, but I don't want to use the x86 instruction set because its simply too much. Is there a basic (but Turing complete) assembler…
Kladskull
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Is it bad that NVCC generates PTX code that is very generous with registers?

I recently read through the generated PTX code of a CUDA kernel. I realized that many registers are used to just store an intermediate value and are then never used again, and that NVCC generally seems to not care much about register re-use and…
Niels Slotboom
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Error: operand type mismatch for `add' immediate value GNU Assembler intel syntax

I tried this simple assembly: add r9, 0x4014000000000000 It gave me error: Error: operand type mismatch for `add' I also try: addq r9, 0x4014000000000000 #(second operand is 64-bit) which q stand for quad 64-bit, CMIIW. I'm sure r9 is 64-bit…
Citra Dewi
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Clarification of some instructions related to LEA and MOV

Why does following occur? *abbreviating r= register, c = immediate value, byte value lea r, [r+c] ;correct as expected mov r, r+c ;error mov r, r+r ;error mov r, [r+c] ;correct mov r, [r+r] ;correct mov r, [c+c] ;correct mov r, c+c ;correct lea r,…
Duke William
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