Understanding jump address calculation for different bit ISA

Question

I am trying to understand how jump address is calculated. So far with the MIPS instruction structure (32 bit ISA), I was able to understand this. Solution after reading through some materials I got was that: Concatenate the following:

1. Upper 4 bits of PC
2. Target address
3. Lower 00s

Now what if I got a different bit ISA say for example 8 bit. Where the J instruction format is given as:

1. Opcode - 2 bits
2. Target address - 6 bits

Will the target address be calculated in the same way or will it be calculated in a different way?

Please help me to understand.

Answer 1

If it wasn't documented, you'd have to reverse engineer the ISA design from some example machine code, or from a working assembler. All commercial ISAs do document how their machine-code works, and so do teaching ISAs where you're expected to work with machine code, not just asm source.

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What we can try to guess based on your proposal:

If there's a 1-byte instruction, then instructions can't be assumed to be aligned to 4-byte boundaries, although it's barely plausible that it would require jump targets to still be aligned. But if alignment isn't required, then you wouldn't be left-shifting the immediate to create an address with the low 2 bits zeroed.

In a 1-byte jump instruction, I'd expect the 6 bits to be used as a relative offset (like MIPS b, e.g. beq $zero,$zero, target), not segment-absolute like MIPS j, because 6-bit segment-absolute would often run into problems where you couldn't jump across some nearby boundary. (64-byte chunks are quite small, and you'd often have a boundary you couldn't j across inside a function.) I assume there'd also be a longer jump instruction with more range, to make it possible to tailcall other functions that are more than -32..+31 bytes away

But of course any design is possible, perhaps even using the immediate as a power of 2 in how far to jump, so you could jump 2, 4, 8, 16, .. bytes forward or backward maybe. Or to that position within a segment. That would be hard to take advantage of, but it's at least possible to design.

I mention that last possibility mostly to make the point that you can't make any assumptions without documentation for the ISA you're working with. (If it's commercially successful, you can often guess that most of the design is sane, but sometimes things that seem insane on their own make sense when considering the design as a whole. Or are just legacy baggage from ancestral designs, as with x86.)