I'm exploring RISCV Priveleged Spec and got confused with memory virtualization (especially hypervisor part and two-stage addr translation).
How can we form Sv57x4 Virtual Address (VA) for G-stage if basic Physical Address (PA) is shorter?
- Sv57x4 VA is 58-bit (Figure 8.43)
- Phys Addr is 56-bit
It wasn't problem for Sv39x4 and Sv48x4, but in this case we are facing literally physical width limit...