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I'm exploring RISCV Priveleged Spec and got confused with memory virtualization (especially hypervisor part and two-stage addr translation).

How can we form Sv57x4 Virtual Address (VA) for G-stage if basic Physical Address (PA) is shorter?

  • Sv57x4 VA is 58-bit (Figure 8.43)
  • Phys Addr is 56-bit

It wasn't problem for Sv39x4 and Sv48x4, but in this case we are facing literally physical width limit...

  • btw, if anybody knows good videos with riscv hypervisor explained - I'll be grateful :) this spec is hell with nuances hiding between the lines. – katzesaal Sep 07 '22 at 04:03

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