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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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What is the actual behavior of the mov instruction?

Suppose you have mov rax, [rsi] from debugging. So, how is this instruction actually executed? Can the address pointed to by the rsi register be the L1 cache in the best case? Or, when the address pointed to by rsi is translated, read data from disk…
initprism
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Can a pointer point to cache memory?

With the mov rax, [rsi] instruction, can the address of rsi point to the L1 cache? Or, when evaluating this instruction, is it possible for the L1 cache hit to fail and point back to the L2 cache?
initprism
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What is an instruction profile?

Here is the statement from my textbook that made me confused as to what "instruction profile" meant: "...new peripheral devices constantly change the nature of the demand on the system in terms of typical instruction profile and the data access…
Job Paulson
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Difference between `CMPXCHG8B m64` and `CMPXCHG r/m64, r64`?

According to https://www.agner.org/optimize/instruction_tables.pdf They are different in zen4 LOCK CMPXCHG, Ops=5, Latency=9 LOCK CMPXCHG8B, Ops=15, Latency=10 instruction reference: // can't see any…
grumpyNeko
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Branch riscv instruction offset calculation on my emulator

I have wrote a riscv64 emulator but I have an issue on offset calculation for branch instructions (especially for bge). For me , the formula to calculate offset to add to pc when condition is meet is : PC = PC+IMM; Immediate is extract from…
riscv_emul
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How to decide if FF instruction is a call instruction or a jmp instruction in X86-64 ELF under linux?

I have such ELF in linux and I disassemble it to do some research. However, I get confused "How to decide if FF instruction is a call instruction or a jmp instruction? For example, the ff instruction occurs like ` 8405de: 48 8b 04 c5 00 81 98 …
yun qi
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Can Cranelift or LLVM IRs be used to develop a simple OS from scratch?

I am curious if I can develop my own programming language to output Cranelift or LLVM IRs, then use it to make a simple OS from scratch? Specifically, do the instruction sets of Cranelift/LLVM IRs contain OS-level IO instructions? Thank you.
geeko
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Is machine code and assembly code part of the architecture?

Is assembly code and machine code specified by the architecture? I know that how you implement the architecutre is uo to you(it is up the microarchitecture can implement the architecture). But I don't understand if the assembly or machine code is…
user394334
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Is carry flag usually cleared after Jump-Not-Carry instruction has been evaluated?

I'm writing a simple simulation of a microprocessor, and, for the JNC instruction, I am unsure if the carry bit is automatically reset after the JNC instruction. Is it (generally, although different cpu architectures might not solve it the same way…
BipedalJoe
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How to find all privileged instructions in AArch64 (ARM-v8) instruction set?

I want to find all privileged instructions in AArch64 (ARMv8) ISA. Currently I can only find privileged instruction list on x86 architecture. How can I find the ones on AArch64? Thank you!
hsyhhh
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Why do we need to Bit Extend the J type instruction to 2 bits only?

Please have a look at this Single Cycle Data Path in MIPS. The 26 bits of J type instruction are being Bit Extended to 28. I don't get the point. Shouldn't it be extended to 31 so it makes 32 bits overall. Please help me out to clear the concept.…
user379888
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Unable to make relation from the diagram

I am given the following diagram with the text. The author refers the AND gate which becomes the control signal PCSrc. But I am unable to make this relation from the diagram. Here is the text, ALU performs comparison of registers in the branch…
user379888
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Clock Cycles per add Instruction

Let's say I have a simple add instruction which needs to add two numbers. I need one cycle too fetch the instruction, one cycle to decode it, two cycles to fetch the numbers, one cycle to add the two numbers and one cycle to write the outcome…
max steuerman
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How do I change the latency of an instruction in gem5?

I could access the latency of the dram but I could not find the latency of the instructions for the matrix multiplication in gem5. I have found the OpClass.hh and the file containing the all the classes but I cannot trace back to the instructions…
User123X
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If a computer has an Intel processor does it mean that it is an x86 machine?

Is it true that every machine that has an Intel CPU is an x86 machine? Considering that all Intel CPU are backward compatible does it mean that every x86 machine is able to run Intel CPUs instruction sets?
Kode1000
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