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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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What is the bit width of a single webassembly instruction?

I know that webassembly currently supports a 32 bit architecture, so I am supposing that, like RISCV32, that its base instruction set has instructions which are 32 bit wide (Of course, RISCV32 supports 16-bit compressed instructions and 48-bit ones…
Waleed Dahshan
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What registers do assembly instructions belong to?

So I'm studying circuit design & I'm trying to determine where the Instruction Set prefixes are registered. surely the computer doesn't understand what mov means. Are they stored on a ROM with the associated logic circuits abstract states (wave…
judofright
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What's differences between address space, addressability, word-addressable, addressing mode?

As far as I know: Address space: the amount of usable memory allocated for program or process Addressability: the way in which computer identifies different memory locations. Word-addressable: refers to a memory unit whose size is equal to "word",…
Eureka
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Understanding address assignment to registers via assembly instructions

If I have a CPU/system with the following characteristics... 16 bit architecture (16 bit registers and bus) 8 total registers A set of 64 assembly instructions And assuming my assembly instructions follow the format... OPCode (6 bits) + Register…
4Matt
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How to load a .word symbol into a register in Arm assembly?

Probably a common beginner question, and similar questions have been asked on this site, but I can't find any help on a couple points. If you have a 32-bit symbol defined with .word, and you want to load it into register r1, what's the conventional…
Sam Gallagher
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Spike simulator ISA error - command not found

having the spike file and the pk file in a folder, when I run this command in terminal: spike -m128 pk archive.x the following error appears: zsh: command not found: spike I don't understand why it doesn't work on my machine but it works on…
GreatField
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Creating New MIPS Instruction

I'm having some problems understanding a question. Consider a proposed new instruction named rpt. This instruction combines a loop’s condition check and counter decrement into a single instruction. For example, rpt $s0, loop would do the…
lionelmayhem
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Behaviour of RISC-V mulh assembly instruction

The RISC-V reader states that mulh rd, rs1, rs2 "multiplies x[rs1] by x[rs2], treating the values as two'cplement numbers, and writes the upper half of the product to x[rd]" So I am trying to multiply two signed 64 bit numbers and get a signed 128…
adrianmcmenamin
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Assembly `mov si, ah` produces "invalid combination of opcode and operands"

So I'm trying to print a character to the screen when I press a key. I get this error: src/kernel/main.asm:20: error: invalid combination of opcode and operands mov ah, 00h int 16h mov si, ah ;where the error is
HoosierTransfer
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how do conditional branches and instructions which update conditional flags operate in an out of order arm architecture?

I have the following sequence of instructions: Address instr Operands 4357128L cmp {"x1", "#16"} 4357132L bne {"4356768"} 4357136L add {"w19", "w6","#16"} 4357140L add {"x0", "x0", "#16"} 4357144L bhi {"4387895"} after cmp…
Tom Jose
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Getting the values of operands for x86-64 given register and memory contents (CS:APP 3e practice problem 3.1)

I need a clarification of a practice problem of Computer Systems A Programmer’s Perspective Third edition. The problem is on page 218 of chapter 3: Practice problem 3.1: Assume the following values are stored at the indicated memory addresses and…
Encipher
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What is the correct way of calculating MIPS?

I found below question about MIPS, A computer system has a CPU with a word length of 64 bits and a clock speed of 1.5GHz. For a certain task, the measured average CPI (cycles per instruction) of the processor is 0.6. What is the MIPS rate of…
Kasun Sampath Weligamage
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RISCV-vector clang causes illegal instruction in spike

I hope you can help me on my RISC-V issue. I am currently experimenting with the toolchain support for RISC-V's vector (RVV) instructions. From what I found on the internet, the spec is currently frozen at v1.0. GCC has a support RVV, but it is not…
Tim H
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Which combinations of operands are legal for these x86-64 instructions?

I am looking for an opinion. I got a fillup the gaps type question in computer architecture for the y86 architecture. movq [a], [b] subq [c], [d] Possible answers are REG $8 %rsp 8(%rsp) -8(%rsp) %rsp Can we solve it as it is when they are not…
Encipher
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How does gpu acceleration work for instructions mot in GPU

I’ve heard that gpus can only compute simple instructions but do them in a parallel matter, which makes them suited for machine learning. What happens if a pytorch tensor is in gpu but the type of computation I want to perform is not included in the…
Danny Han
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