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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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ARMv8-a GNU assembler error : immediate out of range at operand 3

I am having trouble performing logical instructions on the ARMv8-a architecture. for example, "and x13, x13, #0x0000CCCC0000CCCC" or "and x13, x13, #0x0A0A0A0A0A0A0A0A" results in an immediate out of range error, but "and x13, x13,…
DAMPER
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SIMD _mm_store_si128 | _mm_storeu_si128 don't storing correctly

I have a string const signed char From[] = { 0b00000000, 0b00000001, 0b00000010, 0b00000011, 0b00000100, 0b00000101, 0b00000110, 0b00000111, 0b00001000, 0b00001001, 0b00001010, 0b00001011, 0b00001100, 0b00001101, 0b00001110,…
faust403
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How does the control unit differentiate between Jr and the other R-type instructions if they have the same opCode?

Since the control unit takes one input which is opCode, Jr and other R type instructions passes to 000000 to control unit. But for Jr, RegWrite must be 0. How does the control unit differentiate between Jr and the other R-type instructions if they…
Salih Erdem Kaymak
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What is the writing instret when IR bit is cleared in mcounteren register?

In RISC-V architecture, there is an instret CS Register which counts the retired instructions. There is an enable bit for this register in another register called mcounteren. The IR bit of this register is controlling the read operation from lower…
Ömer GÜZEL
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how ALU Function code defined in RISC-V ISA?

In 'Computer Organization and Design' RISC-V version (by Patterson and Hennessy) ebook p1195, it has ALUControl module : module ALUControl ( ALUOp, FuncCode, ALUCtl ); input [1:0] ALUOp; input [5:0] FuncCode; output reg [3:0]…
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When using x86-64 instructions what is the best way to check for their availability without wiping out their entire performance benefit

I am writing some simple D (DLang) wrapper routines around various x86_64 instructions using inline asm. This is working well, but if I want to have an alternative path for older processors where whatever instruction is missing then the overhead for…
Cecil Ward
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Why does RISC-V 'J-immediate' encode imm[11] in inst[20]?

Recently I was learning 'Computer Organization and Design RISC-V' book by David A. Patterson, and was stuck by some questions. Why RISC-V 'J-immediate' put imm[11] in inst[20] instead of inst[24]? Is it related with detailed circuit design, if so,…
zg c
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Why does x86 jump to a new address starting from the PC pointer's tail instead of the header's address?

in x86 why call or jump to another addr is start calucate from nows pc pointers tails address notfrom headers address? maybe x86 has instruction prefixs？ can somebody tell me please？ the reason or some manpage like doc?
Detective玉砌雕栏改
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Does FADDP ST(0), ST(1) make sense?

I have a question: does the FADDP ST(0), ST(1) instruction make sense in the assembly language? As far as I know, in this instruction, we add ST(0) and ST(1) and write the result to ST(0), after which ST(0) gets deleted.
Dan
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When to use a block or a loop in webassembly?

It seems like blocks and loops can be synonymous to each other block $loop foo br $loop end Here the branch instruction would transfer the control to the end which acts like a "break". In case of a loop, loop $loop foo br…
0xfffe
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Program implementation with using specific CPU instructions

I want to realize following steps: unsigned c = 5 c=c*5 I must do this by using this architecture and using 3 instructions at MOST: CPU Architecture Sample instructions for the cpu are like: instructions Extra info about the problem: Suppose that…
Say God
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STM32 sometimes hardfault on reboot (thumb instruction issue?)

STM32L496 micro is hard faulting when power is cycled, but only on some builds of firmware, others are ok. I've been able to track it down to a specific path in the assembly, what looks like is happening is a vector table address is loaded into R3…
Nick Fritz
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What is the effect of nop instruction in instret CSR (in RISC-V architecture)?

In the RISC-V spec, there is a CSR called instret and variants of it for the privilege modes. The spec says that instret is the number of retired instructions. I wonder about the effect of nop instruction on this register because it is not an…
Ömer GÜZEL
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What is the difference between z extend and cast in LLVM

I need to turn the result of a comparison into an i32. The clang compiler with optimizations seems to favor z extend. What do the z extend or s extend instructions do, and especially how are they different to cast? Which should I prefer?
jzimmerman
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Z80 16-Bit Load Instruction and Endianness

I'm writing a ZX Spectrum emulator in C# "for fun" (I think I regret starting already). I know the Z80 is little endian, so in RAM the low-order byte is stored first. What I can't seem to find a definitive answer to, is how it behaves with a 16-bit…
Stevo
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