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I want to realize following steps:

unsigned c = 5
c=c*5

I must do this by using this architecture and using 3 instructions at MOST:

CPU Architecture

Sample instructions for the cpu are like:

instructions

Extra info about the problem:

Suppose that the program is stored in instruction memory starting at address 0, and that each address in the memory holds a single 16-bit instruction. Assume that each CPU register has a starting value of 0xFF and is 8 bits wide. Assume that variable "a" is mapped to the R0 register in the program below and that R1 is used as a temporary register for calculations.

I tried many ways but in all ways i used more than 3 instructions.

extra: datapath

marc_s
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Say God
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    If you tried many ways, why not show your best one or two? FYI, the CPU diagram doesn't shed much light on the complete instruction set, and a sampling of instructions doesn't help much either; for example, we don't know if there is a multiply instruction. However, any reasonable compiler would do the multiplication at compile time and generate runtime code for the value 25 (were variable `c` not eliminated as unused). – Erik Eidt Apr 05 '23 at 16:44
  • dear Erik,Firstly thank you for your comment. best solution i found is that using 1 NOT( to make the register 11111111 to 00000000), 4 ADI ( to make the c value 25). I think this doesnt look meaningful and i did not want to mention it. Sorry for that. My professor claims that by looking these pictures I have to understand the instruction set. (i added one more pic at the bottom of my question). – Say God Apr 05 '23 at 17:06

1 Answers1

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Let's do some analysis of what we can see.

Let's analyze the ADI instruction.  If, say, a 5 bit unsigned immediate is allowed we could simply add 26 to the pre-existing -1 to get the 25 in one instruction.

So, our question is what are the possible immediate values allowed?  To answer this, we can look at the definition in RTL of ADI, which is R[RD] = R[RS] + zf I(2:0).  This says that there is an immediate field encoded in the low three bits of the instruction.  The RTL also suggests that the 3-bit immediate field is zero filled or zero extended, suggesting that field encoded values 0 to 7 mean operand values of the same.  (If it hinted toward sign extension of the 3-bit immediate, that would imply a range of -4 to 3.)

In one diagram there's a shifter near the ALU.  It takes an H input of 2 bits, which I take as an encoding for the shift amount.  (This is almost certainly encoded in the low 2 bits of the instruction for shifting, similar to how the immediate is encoded in the ADI' instruction.)

(Given such a small field, 2 bits, it is silly to waste an encoding with a meaning of shift by 0 bits.)

For the 2-bit field, we have the possible encodings and their meaning that we're guessing at.

Instruction Encoded Value Possible meaning (A) Possible meaning (B)
00 shift left by 1 shift left by 1
01 shift left by 2 shift left by 2
10 shift left by 3 shift right by 1
11 shift left by 4 shift right by 2

Either way, with an educated guess, it looks like it can shift left by either 1 or 2 bits.  (In fact shifting left by 1 bit is potentially a silly encoding choice since that can be accomplished with addition to self.)

So, armed with that analysis of the potential instructions, can you try some more alternatives?

Erik Eidt
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  • I guessed the shifter's 2-bit control might select left/right logical, right arithmetic, or rotate in one direction, all one bit shifts. But yeah, multi-bit shifts are also possible. I guess the instruction-set listing must be partial since it doesn't include anything that would use the shifter, unless address-generation does that. – Peter Cordes Apr 05 '23 at 19:51
  • If we already had an input in one register, we could multiply by 5 in three `add` instructions, two to double it twice to get `c*4`, then adding the original `c`, since it's a 3-operand ISA with a non-destructive separate destination. (Big waste of bits vs. more registers for most real-world programs, but convenient for toy programs with only a couple live variables.) – Peter Cordes Apr 05 '23 at 19:52