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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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What address I could access with LDR instruction of ARM

I'm totally new for ARM assembly code. I just checked the instruction set and found there is an instruction LDR which could be used as "LDR{}{} Rd, ". I have two questions about this instruction: 1) Is the address here physical address or virtual…
S.Wan
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Opcode and funct code in MIPs Assembly

My professor takes forever to answer emails, reasonably so since its Saturday, so I just wanted to ask here instead. I read here that the funct code defines what the function being used is (add, sub, etc) and the opcode defines the format…
Carson Wood
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Using registers and variables in 8086 asm programming

I am starting to get to grips with asm programming but I feel I am missing something regarding the use of registers to store variables. The issue that I have is that some instructions will modify other registers for internal reasons. In some cases I…
Garry Taylor
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What is the simplest Turing complete CPU instruction set which can execute code from ROM?

I believe that all the OISCs below, require that programs are executed from RAM, in order to be Turing Complete. https://en.wikipedia.org/wiki/One_instruction_set_computer Is this the case? What is the simplest Turing Complete CPU instruction set…
fadedbee
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how would I implement a certain instruction in MIPS?

I need to implement an instruction in MIPS assembly that jumps to a location stored in a register if its value is non-negative; otherwise, it jumps to a location stored in a second register. I'm having an issue with how to check for negative values…
zeta
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About arm pc value in thumb 16/32bits mixed instructions stream

I read a couple of articles including question here in SO Why does the ARM PC register point to the instruction after the next one to be executed?, that pc register value is actually current executing instruction address plus 2 instructions ahead,…
Bill Randerson
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What happens when executing an illegal NEON instruction in thumb2 elf?

Say we have an thumb2 elf file with following disassemble snippet by objdump: 00279ae0 : 279ae0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 279ae4: 4606 mov r6, r0 279ae6: f8df 9338 ldr.w r9,…
Bill Randerson
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Instruction set extensions and how software is optimized for those

something bugged me about the instruction set extensions and the possible optimization of software for those. In the wikipedia article about the X86 instruction set is a chroniconal list of extensions, like MMX, SSE or AVX. I know i have to…
user2621742
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g++ dumped assembly output doesn't work

I have following C++ code in main.cpp file. int add(int a,int b) { int c = a + b; return c; } int main() { int a = 2; int b = 4; int d = add(2,4); } when I ran g++ -S main.cpp I got the following assembly code.(after removing…
sampath
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ARM v7-M Instruction Set Decoding Function

Is there any instruction decoder for the ARM v7-M Instruction Set, that I can just give it an opcode as parameter and return me with the corresponding instruction type? For example: MOV Rd, has four different versions depending on the…
Kyriakos
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Instruction Encoding relating to MARIE Assembly language

I am dealing with the following problem: A 1 address computer is one whose instruction can contain at most one operand address. MARIE is an example of such a computer. Typically each instruction is stored as a single word in the memory. Assume the…
JmanxC
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Questions about adding jal instruction to mips single cycle datapath

I am trying to add jal instruction i understand how it works however i am having difficulty implementing it in the hardware? I have this schematic and it shows that 31 connects to the mux before the register but not sure what to connect. I see…
user998316
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MSP430 JC, JNC , JEQ and JNZ

I was looking through the MSP430's instruction set and stumbled upon something I can't quite understand. I can't seem to differentiate what the difference between JC and JNZ and JNC and JEQ. I understand the functions of JEQ and JNZ, but I'm a…
Alan W
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The meaning of the acquire release fence abstract instruction realization of different platform

See the following code: // sparc RMO ia64 x86 // --------------------------------------------------------------------- // fence membar #LoadStore | mf lock addl 0,(sp) // …
yangyixiaof
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8 Register Machine with 4 2-operand instructions in 8-bit format

I'm studying Microprocessors and interfacing at uni and I've come across a very difficult question to get my head around. "Can you design an 8-bit instruction format that cal allow 4 2-operand instructions for a machine with 8 registers" I'm not…
Jordan
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