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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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In buildroot, how to enable deprecated features?

I have to compile C for mips that uses MIPS1 instruction set, but Buildroot no longer supports MIPS1 instruction set (See the bottom of this page: http://buildroot.org/downloads/manual/manual.html). Could you please let me know how to enable the…
freddy
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ARM/Thumb-2 instruction set and assembly

First of all, I'm new when it comes to ARM assembly. I actually have some pieces of code written for ARM instruction set, but my target is a Cortex-M4 architecture using Thumb-2 instruction set. Do I have to re-write the whole code, change some of…
Zohra-tl
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_mm256_xor_si256 for xoring two regions meets a core dump error

For fast XORing two regions of memory, I wrote a function(region_xor_avx()) with AVX instructions optimized. However, the program met a core dump error at _mm256_xor_si256(). Here is a short self-contained example: #include #include…
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how to allocate memory to store register number?

I learned that a register field to specify one out of 64 registers takes 6 bits. since 64 = 26 but don't we have to consider the right most bit ?, which is 20, in which case we require 7 bits to specify one out of 64 registers..
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List of Instruction Sets for Android

In an app I am developing, I need to use a C library. This means I'm going to have to deal with all the different instruction sets of all the different Android devices, right? Is there any list available (or maybe somebody can just tell me?) of all…
Zero
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Fetch steps and execute steps

Recently I am doing some self-study about CPU. And I find a exercise question from the book, since the structure of the book is messed up, I am not able to solve this question. Instruction, Sub[60][61],copies number stored in address 60 to address…
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Two Nands Make an And

I wrote an algorithm for computing the multiplication of two binary numbers. In my instruction set, there is no and instruction, just a nand(not and). I read and it logically makes sense that two nands make an and. I feel this is really simple and…
James Wilks
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Byte Manipulation for MIPS instruction set

I would like to do some byte manipulation using MIPS instruction set. I have register $S0 which has 0x8C2E5F1E and register $S1 which has 0x10AC32BB. I would like to store the second byte of $S0, 5F, into the third byte of $S1, AC. My logic would…
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Complex Instructions and Pipelining

I am reading Computer Organization and Design by P&H and came across the following line: "in an instruction set like the x86 where instructions vary from 1 byte to 17 bytes, pipelining is considerably more challenging", where the comparison being…
vrume21
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What is instruction set encoding?

When designing a process Virtual Machine , the initial consideration that you make is the instruction set encoding. Could someone please explain what this exactly means without going too much into compiler construction or computer architecture.I…
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Difference between "load word" and "load linked word" in MIPS

I am wondering if somebody could explain to me the difference between the LW (load word) and the LL (load linked word) instructions are in MIPS? I cannot seem to find any online sources that distinguish the two from each other and my book does not…
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What are the "dubious" GPU features mentioned here?

From a history of graphics hardware: Indeed, in the most recent hardware era, hardware makers have added features to GPUs that have somewhat... dubious uses in the field of graphics, but substantial uses in GPGPU tasks. What is the author…
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What 2 Mips assembly instructions would induce exactly 2 stalls?

I am using the Mips instruction set architecture and the WinMips64 simulator. My question is when forwarding is deactivated what 2 instructions would produce the 2 stalls, and then when forwarding is enabled produce 0. I would also like to know how…
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OpenSSL ECC gf2m modification to apply PCLMULQDQ instruction

I'm trying to modify OpenSSL code in order to use the PCLMULQDQ instruction to accelerate gf2m operations, as described in the Intel white paper Intel Polynomial Multiplication Instruction and Usage for Elliptic Curve Cryptography The paper…
Chiara Hsieh
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Intel instruction set: multiply with EAX, EBX, ECX or EDX?

How do you suppose to know that when 'mul ecx' was executed. ECX would be multiplied with EAX? And not with EBX or EDX? mul ecx, eax would make more sense though.
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