See the following code:
// sparc RMO ia64 x86
// ---------------------------------------------------------------------
// fence membar #LoadStore | mf lock addl 0,(sp)
// #StoreStore |
// #LoadLoad |
// #StoreLoad
//
// release membar #LoadStore | st.rel [sp]=r0 movl $0,<dummy>
// #StoreStore
// st %g0,[]
//
// acquire ld [%sp],%g0 ld.acq <r>=[sp] movl (sp),<r>
// membar #LoadLoad |
// #LoadStore
//
// release_store membar #LoadStore | st.rel <store>
// #StoreStore
// st
//
// store_fence st st lock xchg
// fence mf
//
// load_acquire ld ld.acq <load>
// membar #LoadLoad |
// #LoadStore
The code above is the realization of acquire/release/fence abstract instruction on different platform,I just want to know the x86 realization.
Can you explain the instructions below for me?
How 'movl $0,<dummy>' represent release?
How 'movl (sp),<r>' represent acquire?
How '<store>' represent release_store?
How 'lock xchg' represent store_fence?
How '<load>' represent load_acquire?
The code is from jdk8/openjdk/hotspot/src/share/vm/runtime/OrderAddress.hpp the 'Memory Access Ordering Model'
If you are busy,you can just tell me where can I find the instruction set information about different CPU architectures.