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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Conditional instructions in AVX2

Can you give the list of conditional instructions available in AVX2? So far I've found the following: _mm256_blendv_* for selection from a and b based on mask c Are there something like conditional multiply and conditional add, etc.? Also if…
Serge Rogatch
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How can I check whether an ISA extension is supported by current ARM CPU?

When a userspace program on x86 needs to determine whether e.g. AVX extension is supported, it can use CPUID instruction. Is there any similarly OS-independent way to check support for an ISA extension (e.g. NEON) in ARM?
Ruslan
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What is the difference between system calls and instruction set

Iam confused whether system calls and instruction set are synonymous? Do the instructions like MOV, LOAD, CALL, IN, OUT , ADD, SUB etc fall in the category of system calls? System call instructions like open(), close(), read(), write(). If not then…
Pranjal Kanyal
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How to choose instructions for a homebrew CPU?

I am designing a minimal home-brew CPU (for fun and learning) capable of addition and subtraction. P->| |---------->P A->| ___ |---------->A 0->|-| | |---------->T |ADD|-|->ROM-->| R->|-|___| |->RAM<->| N->| |->R …
fadedbee
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C to assembly - leaq instruction

As far as I understood: %rdi = 1st argument = x %rsi = 2nd argument = y %rdx = 3rd argument = z The others manipulate these registers... and store in a return value register The 3rd line on the assembly code leaq (%rsi, %rsi, 2), %rdx, which as I…
dud3
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How to compute Stack usage on TI processor from the LST files?

The .lst file gives FR SIZE for each function used in the code. Can I consider that as the stack usage in Words? I am trying to find any supporting document for this, but in vain.
Yutha
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Heap pointer register?

Many ISAs, such as MIPS, has a register called "stack pointer" to indicate the top of the stack. Why isn't a "heap pointer" register? Does the top of the heap get stored in memory?
xri
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A simple MIPS, question

I have a question, which is kind of confusing Write the MIPS instruction whose machine language encoding is: 0000 0011 0001 1001 0100 0000 0010 1010 Your answer must use register names (like $t0) not numbers; and must specify any immediate as a…
smooth_smoothie
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Defining and Using Global Variable in PowerPC Assembly file

I want to save the contents of a SPR ( Special Purpose Register ) to a global variable. I don't have much experience in Assembly, but i tried to do it as follows : .global __The_Global_Variable mfspr r16, 695 #695 is the number of the SPR…
Maged Rawash
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Are Kernel functions/x86 instructions outw and inw atomic when accessing ISA/LPC?

tl;dr Are Linux kernel functions outw() and inw() atomic when accessing ISA/LPC on x86 on a multicore system, given that at a HW level it must consist of four separate 8-bit transactions? As an equivalent question, since outw() and inw() functions…
Damien
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Difference between implied and immediate addressing mode?

Implied: operands are specified implicitly in the definition of instruction. Examples: CLA,CME,INP. It is mainly used for Zero-address (STACK-organized) and One-address (ACCUMULATOR-organized) instructions. Immediate: operand is specified in the…
Kamal Pratap
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Multiple ISA in same ELF file

Is it possible to have an ELF file that contains executable instructions from two ISAs. That is have a single ELF file that can be run on two architectures, say a x86 and a PowerPC. One example of this that comes to mind was the Apple Universal…
ssb
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why is a vdiv instruction generated with neon flags?

I disassembled an arm binary previously compiled with neon flags: -mcpu=cortex-a9 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize The dump shows a vdiv.f64 instruction generated by the compiler. According to the arm manual for armv7 (cortex-a9) neon…
raul garcia
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Assembler mov issue

I have the next code: mov ax,@data mov ds,ax Why I can not write just like this? mov ds,@data All source: .MODEL small .STACK 100h .DATA HelloMessage DB 'Hello, world',13,10,'$' .CODE .startup mov ax,@data mov ds,ax …
Alex Pliutau
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Need Clarification on Memory Accessing (ISA/MIPS)

I'm doing a theoretical assignment where I design my own ISA. I'm doing a Memory-Memory design where the ALU receives inputs from memory and outputs back to memory without using any registers. This is an outdated method and registers are more…
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