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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Trouble Figuring out loading to register with offset from different register

I am creating an 8-bit CPU. I have basic instructions like mov, ld, st, add, sub, mult, jmp. I am trying to put my instructions together. First I move the base address of a value into register 1 (R1). I then want to load register 2 (R2) with the…
new_programmer_22
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How did the legacy 3DNow! instruction set store results to memory or integer registers?

Just for fun I'm reviewing legacy (deprecated) instructions from 3DNow! set introduced by AMD, and I'm trying to understand how were they used. All instructions seem to be encoded following this pattern: instruction destination_MMn_register_operand,…
MikeF
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How to define the length of a vector prior to using x86 SSE assembly instructions?

Is there a register than contains the number of elements in a vector/array that I must load prior to using an operation like mulss or addss, or perhaps do I have to push that number on the stack? How do SSE instructions know the length of the…
annoying_squid
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How do you convert little Endian to big Endian with bitwise operations?

I get that you'd want to do something like take the first four bits put them on a stack (reading from left to right) then do you just put them in a register and shift them x times to put them at the right part of the number? Something like 1000…
Heinz
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What control lines are asserted/set to 1 when a load double word instruction is called?

Using this diagram, I am looking at this instruction to determine what control lines are necessary. ld x5, 40(x9) x5 = 0x000000ff x9 = 0x00000fff I am curious what control lines (RegWrite, MemRead, MemWrite, MemtoReg, Branch, Zero, ALUSrc) are…
Megan Byers
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RISCV Instruction set simulator

I'm look for instruction set simulator for CPU based on RISC-V. I want to observe the hazard on different CPUs (RISCV and MIPS). This example is for MIPS. lw r1,A(r2) lw r3,B(r4) dadd r5,r1,r3 beq r5,r5,L1 sw r5,A(r3) L1: sw r5,B(r4) beq must be…
Barry
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Pushing imm32 ends up in pushing imm64?

From the intel instruction reference: 68 id PUSH imm32 It means pushing dword-sized immediates is valid in 64-bit program. So I wrote the following program: section .text global _start _start: call _foo mov rax, 60 …
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which mode in intel x86-64 is faster to execute instructions

Intel has - real mode - protected mode - virtual real mode - 64-bit mode Out of these modes, which one execute the same sets of instructions faster? using prefixes one can change the addresses & sizes that can similar to other modes.
Lakshman Siddardha
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Backward compatibility of the code compiled optimized for new instruction set extensions

In order to narrow the scope of this question, let's consider projects in C / C++ only. There is a whole array of new SIMD instruction set extensions for x86 architecture, though in order to benefit from them a developer should recompile the code…
Pavel
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Direct Arithmetic Operations on Small-sized Numbers in RISC Architectures

Are there any RISC architectures which allow arithmetic operations to be applied individually to bytes, half-words and other data cells, whose size is less than the size of the CPU general purpose registers? In Intel x86 (IA-32) and x86-64 (known as…
Victor
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How can an understanding of the ARMv7 Architecture lead to more efficient Java/Android code?

I am watching many videos and reading some articles on RISC and CISC architectures and Computer Architecture in general. To my limited understanding, one major difference between RISC and CISC is: each RISC instruction roughly translates to a…
Sam Hammamy
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Is this MARIE instruction set even possible?

I was given the following MARIE instruction set and told to output what the symbol table was for the first pass, and the result in the AC. The problem is, I don't even think this is possible: Hex Address Label Instruction 100 Start,…
Armani
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How to use the enhanced multiplier instructions of ARMv5TE instruction set

I'm using an ARM966E-S RISC-CPU and was wondering how to use the apparently available instruction set extensions for better DSP performance, e. g. an enhanced multiplier instruction. I've read in the technical reference manual that these instruction…
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Where is an ISA stored and how exactly is it taken into account?

I'm studying what makes a computer a computer So far I understood that we have High-Level programming language -> -> Compiled into low level programming language (assembly language) -> -> Which the assembler then uses to send instructions directly…
Adelin
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How to find the time value of operation to optimize new algorithm design?

My question is specific to iPhone, iPod, and iPad, since I am assuming that the architecture makes a big difference. I'm hoping there is either a specification somewhere (for the various chips perhaps), or a reliable way to measure T for each…
Rab
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