Difference between implied and immediate addressing mode?

Question

Implied: operands are specified implicitly in the definition of instruction. Examples: CLA,CME,INP.

It is mainly used for Zero-address (STACK-organized) and One-address (ACCUMULATOR-organized) instructions.

Immediate: operand is specified in the instruction itself and mainly for constants . Example: ADD R1,#3 ,MUL R1,R2,#7

but the question comes how to check the instruction:

1) PUSH 3

and

2)LD 7

First one is a zero address instruction (Stack based) and the second is an accumulator instruction. In both instructions the operand is defined in the instruction itself. Which addressing mode is preferred, or best describes them?

How to check whether the instruction is implied or immediate?

Further examples of implicit operands on x86: SAHF, LAHF, and CPUID.

source: https://en.wikipedia.org/wiki/CPUID

In assembly language the CPUID instruction takes no explicit parameters as CPUID implicitly uses the EAX register (and sometimes ECX) to determine the information returned in EAX,EBX,ECX, and EDX.

source: http://www.felixcloutier.com/x86/LAHF.html

LAHF — Load Status Flags into AH Register
This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.

source: http://www.felixcloutier.com/x86/SAHF.html

SAHF — Store AH into Flags
Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved bits (1, 3, and 5) in the EFLAGS register remain as shown in the “Operation” section below.

This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.

usage example: (source: https://www.slideshare.net/rbtaccess/flag-control )

MOV AH, 25H       ; immediate source operand
SAHF              ; implicit operands

more examples include CLC, STC, and CMC, which clear, set, or flip the carry flag CF respectively. (CF is a bit in FLAGS, not a whole register.)

*How to check whether the instruction is implied or immediate?* That doesn't really make sense. You have to look at each operand separately, not the whole instruction. e.g. PUSH implicitly stores to the stack, but its explicit operand can be a register, or immediate. On some architectures, like x86, PUSH can even accept a memory operand. [`PUSH r/m32`](http://www.felixcloutier.com/x86/PUSH.html) is one opcode, and the addressing mode selects between memory or register source. — Peter Cordes, Sep 01 '16 at 06:49
@Peter if the instruction is `PUSH A` the operand is in memory then is it implied mode because the operand is not the ACTUAL OPERAND ? — Kamal Pratap, Sep 01 '16 at 06:55
@PSPCODER: this question is clearly about some kind of accumulator architecture, where that operand is always implicit. Replacing most of the question with x86 examples is not appropriate. Your edit would work better as an answer, or possibly a separate section to the question *after* the original text. — Peter Cordes, Sep 06 '18 at 01:42

Peter Cordes · Answer 1 · 2018-09-06T02:08:26.347

An instruction like PUSH has two operands: the implicit destination and the explicit source. That explicit source can be a register, an immediate, or (on some ISA like x86), an explicit memory operand like push qword [rdi + rax*8].

Implicit, register, explicit-memory, or immediate is a property of an operand, not the whole instruction.

You can't label the whole instruction as using either implicit or immediate. You could talk about just the source operand being implicit vs. immediate for some simple accumulator ISAs, but your question also showed what looked like ARM instructions as examples of immediate.

An instruction where all the operands are of the same category could be said to use implicit operands, for example. e.g. x86's movsd instruction has two operands, and both are implicit memory operands. (It copies from [rsi] to [rdi], and increments both pointers. Or decrements according to DF, so that's another implicit input).

x86's inc instruction has only one operand, which can be register or memory. (Actually FLAGS is an implicit output operand, like for most x86 instructions).

push 3 decrements the stack pointer and stores to memory (using the new value of the stack pointer as the address). This is true on x86, and many other architectures (stack grows down and points to the last thing pushed).

So if we want to get into the full details, push imm8 has the following operands:

implicit read/write register operand: the stack pointer (rsp)
implicit memory destination: [rsp]
immediate source value: the 8-bit source, sign-extended to 64-bit.

We're ignoring x86 segmentation, or we could count ss as an extra implicit input operand, along with rsp).

Why is this answer getting downvotes? Each operand has one addressing mode; whole instructions can have more than 1. I don't see anything wrong with this answer, and IMO it's still a better answer than the others. — Peter Cordes, Jun 30 '18 at 15:57
You're on every question lol. Yes, the write to `rsp` is 'implied register addressing' of `rsp` and then write to `[rsp]` would be like 'implied register indirect addressing ' and then imm8 is 'immediate addressing'. If addressing were applicable to the whole instruction / opcode then push would be 'implied register implied register indirect immediate addressing' which is nonsense. `push rbp` you could call `rbp` 'register addressing'; it's not really implicit, but there is only an opcode byte.. `Implied addressing refers to instructions that comprise only an opcode without an operand` — Lewis Kelsey, Apr 01 '20 at 16:42
@LewisKelsey: Yeah, you could look at `push reg` as 8 separate push-implicit opcodes, or as one opcode that leaves room for a 3-bit explicit `reg` field. Given the interaction with REX.B to encode `push r8..r15`, I think the explicit interpretation makes more sense (for the source operand) in most ways of looking at it. https://www.felixcloutier.com/x86/push says `50+rd` for the encoding. It calls the table field "opcode", but really it's the encoding for the whole instruction like `6A ib` for `push imm8` — Peter Cordes, Apr 01 '20 at 16:50

score 2 · Answer 2 · answered Oct 31 '17 at 15:17

Implied: Not specified directly. Operands address are not explicity specified.

Take Zero address of Stack organization for an example.

ADD

Here operands are not directly specified. The two top elements of the stack are popped and then added. Note the operands are not directly present in the instruction. IMPLIED

Immediate: This is quite simple, operands are direcly present in the address field. Address field is more like operand field.

score 2 · Answer 3 · edited Jun 26 '18 at 19:22

Implied Addressing Mode:
Implied Addressing Mode also known as "Implicit" or "Inherent" addressing mode is the addressing mode in which, no operand(register or memory location or data) is specified in the instruction. As in this mode the operand are specified implicit in the definition of instruction.

As an example: The instruction:“Complement Accumulator” is an Implied Mode instruction because the operand in the accumulator register is implied in the definition of instruction.In assembly language it is written as:
CMA: Take complement of content of AC
Similarly, the instruction,
RLC: Rotate the content of Accumulator is an implied mode instruction.

In addition to this, all Register-Reference instruction that use an accumulator and Zero-Address instruction in a Stack Organised Computer are implied mode instructions, because in Register reference operand implied in accumulator and in Zero-Address instruction, the operand implied on the Top of Stack.

Immediate Addressing Mode:
In Immediate Addressing Mode operand is specified in the instruction itself.In other words, an immediate mode instruction has an operand field rather than an address field, which contain actual operand to be used in conjunction with the operand specified in the instruction.That is, in this mode,the format of instruction is:

As an example: The Instruction:

MVI 06 Move 06 to the accumulator
ADD 05 ADD 05 to the content of accumulator

In addition to this , this mode is very useful for initialising the register to a constant value.

If a CPU with a `CMA` instruction also had an instruction to complement some other register, you could say that it had an explicit destination. (Actual CPUs with an accumulator often have a couple other registers besides the accumulator, e.g. some 16-bit pointer regs separate from an 8-bit AC. They usually support a few operations on them, like increment, but not as many as on AC). Or maybe you'd say that both instructions were unrelated and had implicit destinations, if their instruction encoding was different, instead of being the same except for a bit or 2 encoding the destination. — Peter Cordes, Jun 26 '18 at 19:26
I'm also not sure this really answers the question, because `MVI 6` also has AC as an implicit destination, and the OP's confusion was about the whole instruction only having a single mode. But pretty good answer anyway, welcome to Stack Overflow. — Peter Cordes, Jun 26 '18 at 19:27

Difference between implied and immediate addressing mode?

3 Answers3