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I am designing a minimal home-brew CPU (for fun and learning) capable of addition and subtraction.

 P->|       |---------->P
 A->|  ___  |---------->A
 0->|-|   | |---------->T
      |ADD|-|->ROM-->|
 R->|-|___| |->RAM<->|
 N->|                |->R
 0->|                |->N
 T------------------>|->I

I is the instruction register. The adder is capable of directly calculating addresses, but can also be used for general arithmetic, though the result must travel via the Temporary register on it's way to RAM.

R is the Read register (red, not reed). N is the iNverted register which is clocked by the same signal as R, but outputs ~R.

It's a little weird, as the address bus is constantly driven by the adder. This data-path configuration was designed to allow useful instruction sequences such as:

fetch: [P++]->I 
addi:  [P++]->R; A+R->A
add:   [P++]->R; [R]->R; A+R->A
load:  [P++]->R; R->A
store: A->T; [P++]->A; T->[A]  // A is clobbered
store: A->T; [P++]->A; T->[A]; T->R; R->A
jump:  [P++]->R; P+R->P
move:  [P++]->R; [R]->T; [P++]->R; R->A; T->[A]

The control system needs to generate the following enable/read signals: Pen, Aen, Ren, Nen, Ten, MEMrd.

Also the following clock/latch/write signals are needed: Pck, Ack, RNck, Tck, MEMwr.

In addition to these, a signal is also needed for Cin (carry-in) for the adder because subtraction is implemented as A - R == A + N + 1, as N == ~R.

There are currently a total of 12 bits of signal, so there are 4096 possible combinations.

How can I calculate which of these 4096 instructions will be of most use, so that I can design decoding logic for the Instruction register?

Is it best just to persevere with implementing an accumulator-machine instruction set, one instruction at a time, or is there a better strategy?

P.S. Conditional instructions are still a work in progress...

fadedbee
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    How many bits do you want to use for your op-code? Is your architecture 12 bits? Or are you saying you're allocating 12 bits to the op-code out of a larger set of bits per instruction? – Julian May 17 '17 at 21:21
  • Opcodes will be 8 bits at most. The proof-of-concept will be have an 8 bit address/alu bus and an 8 bit data bus. At most, I will have to select 256 out of 4096 combinations to decode, but I expect that I will need a couple of instruction bits for flags/conditions, so I'll have to select just 64 of the 4096 combinations. The 8->12 bit (I->signals) decoder may be a ROM, but hopefully just some 74HC logic, if I can find enough regularity in the subset. – fadedbee May 17 '17 at 21:28
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    If I understand correctly, you will want to consider what instructions you want available to you cpu. The quantity of those instructions will be much less than 4096. The more bits you dedicate to your op-code, the fewer bits you have per instruction to actually use as user or program supplied data. Some 16 bit architectures I've seen use 4-bit op codes which leaves 12 bits left over for the instructions to use. The more bits you don't use in your op-code, the greater distance for example you can reference in memory from your current PC location. – Julian May 17 '17 at 21:30
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    Yes, exactly, I want to find which 64 (or less) instructions from the 4096 combinations are most useful/critical. – fadedbee May 17 '17 at 21:31
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    I think the combinations that are useful are going to be very specific to the architecture you're designing. Your cpu will take instructions coming in, and branch based on that op code (not instruction branching), so it can make sense to pivot types of instructions that share similar physical pathways on the same bit for example. And what shares similar, or different pathways, depends on how you've laid it all out architecturally – Julian May 17 '17 at 21:32
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    Have you made any progress on this? I'm looking forward to hearing your results and what you learned along the way – Julian May 24 '17 at 23:33
  • @JulianCleary Yes, a little, mostly to do with microcode a conditionals. Do you think that this project is worth documenting as I proceed? (Probably a GitHub page, or maybe hackaday.io.) – fadedbee May 25 '17 at 12:22
  • That's a good idea. This is a topic that isn't touched on often enough. I think that this project has potential to be a very interesting read :) – Julian May 25 '17 at 16:59

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