I am designing a minimal home-brew CPU (for fun and learning) capable of addition and subtraction.
P->| |---------->P
A->| ___ |---------->A
0->|-| | |---------->T
|ADD|-|->ROM-->|
R->|-|___| |->RAM<->|
N->| |->R
0->| |->N
T------------------>|->I
I
is the instruction register. The adder is capable of directly calculating addresses, but can also be used for general arithmetic, though the result must travel via the T
emporary register on it's way to RAM.
R
is the Read register (red, not reed). N
is the iNverted register which is clocked by the same signal as R
, but outputs ~R
.
It's a little weird, as the address bus is constantly driven by the adder. This data-path configuration was designed to allow useful instruction sequences such as:
fetch: [P++]->I
addi: [P++]->R; A+R->A
add: [P++]->R; [R]->R; A+R->A
load: [P++]->R; R->A
store: A->T; [P++]->A; T->[A] // A is clobbered
store: A->T; [P++]->A; T->[A]; T->R; R->A
jump: [P++]->R; P+R->P
move: [P++]->R; [R]->T; [P++]->R; R->A; T->[A]
The control system needs to generate the following enable/read signals: Pen
, Aen
, Ren
, Nen
, Ten
, MEMrd
.
Also the following clock/latch/write signals are needed: Pck
, Ack
, RNck
, Tck
, MEMwr
.
In addition to these, a signal is also needed for Cin
(carry-in) for the adder because subtraction is implemented as A - R == A + N + 1
, as N == ~R
.
There are currently a total of 12 bits of signal, so there are 4096 possible combinations.
How can I calculate which of these 4096 instructions will be of most use, so that I can design decoding logic for the Instruction register?
Is it best just to persevere with implementing an accumulator-machine instruction set, one instruction at a time, or is there a better strategy?
P.S. Conditional instructions are still a work in progress...