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enter image description here]Using this diagram, I am looking at this instruction to determine what control lines are necessary.

ld x5, 40(x9)

x5 = 0x000000ff

x9 = 0x00000fff

I am curious what control lines (RegWrite, MemRead, MemWrite, MemtoReg, Branch, Zero, ALUSrc) are asserted or set to 1 in order for this instruction to run, and why I understand the parts of the load double instruction to be ld RT, Disp(RA) - but what is required for execution and why? Thank you - resources on these things (that make sense to me) are extremely limited on the internet.

Peter Cordes
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Megan Byers
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  • This appears machine specific, I think you might need to specify the particular hardware for context. – AnOccasionalCashew Mar 07 '18 at 04:05
  • I'm not sure how to determine this - I can use this diagram to come to a conclusion, I added a photo. We are learning about URISC and R-type instructions, if that helps – Megan Byers Mar 07 '18 at 04:10
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    Do you have a URL for the URISC architecture you're learning about? The top google hits for `urisc architecture` are for one-instruction-set architectures (which only have one opcode, often something like subtract and branch if less or equal.) e.g. https://cs.uwaterloo.ca/research/tr/1987/CS-87-36.pdf. But that's obviously not what you have, because you describe an `add` instruction (with register names that look like MIPS). But then in the text you have register names like x9, which looks like AArch64. And different implementations of AArch64 are possible. What is this question about? – Peter Cordes Mar 07 '18 at 04:32
  • Here is a link to my textbook: http://ac.aua.am/Arm/Public/2017-Spring-Computer-Organization/Textbooks/ComputerOrganizationAndDesign5thEdition2014.pdf . The figure is on page 266. I posted an image of the exact question it's asking - it's entirely possible it's MIPS architecture, but I'm really unsure on how to recognize these things! Thank you – Megan Byers Mar 07 '18 at 04:41
  • Pretty sure it's MIPS based on saying "R-type instruction", and that MIPS is by far the most common architecture for classes like this to ask questions about the internals. And `ld` is the right mnemonic for doubleword-load, so it's just the register name that's odd. MIPS is not a URISC, it's an ordinary RISC with a fairly rich instruction set. But it is designed to have no microcoded instructions, and otherwise be possible to implement without a lot of transistors. Especially designed for a pipelined implementation, which this appears *not* to be. – Peter Cordes Mar 07 '18 at 04:49
  • Do you have any suggestions on how I can find the control lines given that it's a MIPs architecture? – Megan Byers Mar 07 '18 at 05:11
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    update: it's a RISC-V https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf. RISC-V has registers called `x`, and R-type instructions. Your diagram's register names like `$t1` and so on would indicate MIPS, though. Anyway, regardless of the name of the architecture, the diagram of the microarchitecture internals should be enough to answer the question. You know what the instruction does, so look at the various signals and decide whether or not any part of that instruction's execution needs that operation. e.g. there's obviously no MemWrite because it's a pure load. – Peter Cordes Mar 07 '18 at 05:36

1 Answers1

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Its a LOAD instruction in which the memory address to be read is calculated by adding 40 to the contents of the register x9, the result is then stored in register x5.

  1. Instruction is writing to registers, therefore assert RegDst and RegWrite
  2. Instruction is required to add 40 to the contents of x5. Set ALUSrc to 1 to select 40 as one of the source.
  3. Assert MemReadas its a memory read. Also set MemtoReg to 1 so that mux will get the data from Memory rather than ALU.
Isuru H
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