RISCV Instruction set simulator

Question

I'm look for instruction set simulator for CPU based on RISC-V. I want to observe the hazard on different CPUs (RISCV and MIPS).

This example is for MIPS.

lw r1,A(r2)
lw r3,B(r4)
dadd r5,r1,r3
beq r5,r5,L1 
sw r5,A(r3)
L1: sw r5,B(r4)

beq must be stall (wait for r5)

Do you suggest any software simulator? I can write some instructions to simulate. For MIPS, I use WinMIPS64 (http://indigo.ie/~mscott/).

score 0 · Answer 1 · answered Mar 13 '18 at 18:36

0

The canonical instruction set simulator for RISC-V is here https://github.com/riscv/riscv-isa-sim

It does not highlight dependencies because it is not modeling a specific CPU but just modeling the ISA.

answered Mar 13 '18 at 18:36

colins

351
1
3

score 0 · Answer 2 · answered Nov 22 '21 at 14:15

Ripes is a graphical processor simulator and assembly editor for the RISC-V ISA. Its current version (ver. 2.2.3) has different versions of the RISC-V processor (single-cycle, 5-stage w/o forwarding or hazard detection, 5-stage w/ forwarding but w/o hazard detection, 5-stage w/ hazard detection but w/o forwarding, 5-stage w/ forwarding and hazard detection, 6-stage dual-issue). Both 32-bit and 64-bit versions of these are supplied.

RISCV Instruction set simulator

2 Answers2