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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Should a semiconductor manufacturer buying IPs from ARM meet the clock cycles for an instruction described in the reference manual?

For the CC3220S manufactured by Texas Instruments, I developed a function in the C programming language which uses inline Assembly to wait 1 second (excluding the instructions before the loop and outside the loop). According to the ARMv7-M reference…
Xhendos
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Why ALU result writes address into memory for R-Type instructions?

I'm trying to understand single-cycle datapath for MIPS instructions. Currently I can trace R-type, I-type and J-type instructions and I'm aware of control signals on different instructions but there are still unclear points in my mind. In this…
patoglu
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How does x86 handle byte vs word addressing when executing instructions and reading/writing data?

So I am learning how x86 works and have come across people saying that it is byte-addressable, yet can read words, double words, etc. How does the processor decide which method to use and when? E.g. for accessing the next instruction and when a user…
kingstoncompsci
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Are two-byte instructions necessary for an 8-bit instruction set architecture?

I am working on designing and implementing a simple 8-bit computer. I intend to have an 8-bit data bus, 8-bit address bus, and 8-bit instructions. I intend to have a RISC style load-store architecture. I am working on designing the instruction set,…
teddyv
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Minimum processor capability to boot Linux

I am in the process of designing a custom processor. It is a pipelined five stage processor. Ultimately, we want to boot Linux on it. What are the minimum capabilities that a custom processor must have in order to boot a full-fledged OS like Linux?…
osama zeeshan
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Difference between FMA and naive a*b+c?

In the BSD Library Functions Manual of FMA(3), it says "These functions compute x * y + z." So what's the difference between FMA and a naive code which does x * y + z? And why FMA has a better performance in most cases?
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By reading .hex and .map, how can I be sure that a BL links to the right function offset?

I'm currently doing an "hex compare" for fun to understand what is happening. I know that comparing hex sometimes gives too much changes to be compared. By just changing a function call, I can make a small change happen in the hex. My embedded code…
Guillaume D
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Getting Illegal Instruction while running a basic Avx512 code

I am trying to learn AVX instructions and while running a basic code I recieve Illegal instruction (core dumped) The code is mentioned below and I am compiling it using g++ -mavx512f 1.cpp What exactly is the problem and how to overcome…
prajjwal_jha
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Processor Design- Hazard management unit

I am designing a cell SPE processor. I have to check for data hazards before I take data from register file. What is the best way to identify the number of stall cycles necessary and what design decisions should I take about where to stall the…
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Is my understanding of lw instruction in MIPS correct?

I am just starting to understand MIPS, and the particular instruction "lw" confuses me. From the thread, Understanding how `lw` and `sw` actually work in a MIPS program, this is what I have gathered: If, say, we have: lw a, 4(b) // a and b are…
Tina
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How is a 15 bytes instruction transferred form memory to CPU?

Assuming we are using a x86-64 machine, it means it's general registers are 64 bits long, its data bus can handle 64 bits at a time, its ALU can handle at max 64 bit number (right?). Having a simple instruction like MOV $5, %eax moves a 32 bit…
John
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How do register numbers affect number of loads and stores in ISA?

I am trying to solve a question about register numbers in instruction set architecture. The question is; Suppose that the code sequence is to compute A=B+C, B=A+C, and D=A-B. Assume that all of A, B, C, and D are initially in memory. List the…
mancini13
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Left Shift Logical by sum of two numbers/registers?

Is there a way to perform a left shift logical by a sum of two numbers/registers? I am thinking of something that looks like this, but actually works: mov r4, r1, lsl add, r7, #1
brunshte
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How do I identify the instruction stored LC-3

I know this is not a programming question but I am struggling to understand how to get the solution to this problem. I'm not sure how this is figured out and I can't find a explained solution.
Janeson00
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CISC short instructions vs long instructions

I'm currently programming a compiler and am about to implement code generation. The target instruction set for now is x64. Now x64 is CISC, so there are many complex instructions. But I know these are internally converted to RISC by the CPU, and…
Richard
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