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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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How does RISC-V variable length of instruction work in detail?

After skimming the RISC-V ISA doc, it gives me the impression that the RISC-V supports both 16-bit(RVC), 32-bit(RV32I), and 64-bit(RV64I) length of instructions. For the RV32I: immediate is signed extended to 32 bits Instruction length:32…
Billy
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How can I limit autovectorization level in GCC?

In other words, is it possible to cap autovectorization instructions (obtained with -fast-math -ftree-vectorize) to something like AVX while still using AVX512 through explicit intrinsic call? At the moment, without -mavx512f, GCC fails saying it…
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Is there an function in AVX512 like _mm512_sign_epi16 (__m512i a, __m512i b)

The following function seems to not be available on AVX512: __m512i _mm512_sign_epi16 (__m512i a, __m512i b) Will it available soon or is there an alternative?
yueluojieying
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Check instruction sets tensorflow build is compiled with

I am looking for a way to confirm that a tensorflow wheel was compiled with the correct instructions. I am trying to build tensorflow for a Intel Atom CPU. I know that bazel will detect and build with appropriate instructions automatically, but I…
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How to convert Stack based instructions to Register based

This is what I have tested with the dis module in python - >>> def f(): ... a = 1 ... b = 2 ... c = 3 ... a = b + c * a ... return a + c ... >>> dis.dis(f) 2 0 LOAD_CONST 1 (1) 2 STORE_FAST …
Dean
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Why does the 6502 microcontroller not have a arithmetic right shift?

I'm trying to understand the instruction sets of old microcontrollers, especially the 6502. The documentation of the instruction set that can be found here lists two shift instructions (beside the rotate instructions): ASL - arithmetic shift…
uzumaki
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Why are the temporary registers split in the MIPS ISA?

I'm currently taking a class that covers the MIPS ISA and one thing that I noticed is the split in temporary registers: Temporary registers $t0 to $t7 are stored in $8 to $15, but $t8 and $t9 are stored in $24 and $25. Why is this? Why not make the…
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Why does RV32I include instructions like ADDI and XORI but not BLTI?

I'm not experienced in ISA design. I've been reading https://riscv.org/specifications/ chapter 2, page 21. Could someone explain why RISC-V has arithmetic and logical instructions which use immediates, such as ADDI and XORI, but not similar…
fadedbee
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Does a processor that supports SSE4 support SSSE3 instructions?

I am developing a hardware platform that requires the SSSE3 instruction set. When looking at a processor such as the Intel Atom® x5-Z8350 the datasheet says it has support for SSE4.1 and SSE4.2. Would this allow software written for SSSE3…
Eric Johnson
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Which is the first CPU that Intel has added conditional move instructions to?

I remember having read about it somewhere… Could anyone shed some light on this?
Ryan Li
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ARM vs x86 What are the key differences?

I am not so much interested to know about the "small print" the differences while developing code on each platform in terms of what a programmer is used to or what he finds easier to do etc. Nor am I interested in the detailed physical differences…
papajo
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Difference between MIPS and ARM datapaths

I have just learnt MIPS architecture in the class. I am reading other Instruction Set Architectures (ARM currently) and found some differences between ARM and MIPS. Both have different instruction formats, register set, etc. Is there any difference…
azhar baloch
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Why are 'opcode' field and 'funct' field apart in MIPS?

MIPS ISA has an R type instruction, and the R instruction has an opcode field at its first 6 bits and a funct field at its last 6 bits. So why are the ISA designed like this? How about combine them into a 12-bits field?
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Does RISC-V mandate two's complement or one's complement signedness, or is it implementation-determined?

I have looked through the ISA spec and searched the internet for the answer to this, but I could not find it. In the RISC-V ISA, should negative numbers be represented with one's complement or two's complement? Or, is this decision left to…
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In which language a BIOS is written?

As I understand, the BIOS code/bitstream that held in the ROM should be generic (work alongside with multiple CPU types or ISAs). In addition, I saw mentions in the web that claim to have the possibility to dump it's code (and to "disassemble"…
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