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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Pipeline refill cycles for instructions in arm

Following are the instructions of arm Cortex M4 processor with 3 stage pipeline.How do we come to know the number of pipeline refill cycle for such instructions?? Assembler Cycles 1. MOV PC, Rm 1 + P 2. …
Manish Gaur
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x86 OpCode Instruction Decoding

I've been looking into the Software Developer's Manual of the x86 architecture trying to brush my reverse engineering skills. I know that the architecture is complex and backwards compatible with previous generations. With newer generations some of…
Nocturnal
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when should I use AESIMC separately, instead of using AESDEC

The x86 ISA allow me to use AES-NI instructions to encrypt/decrypt all 4 steps of a round together, or only 3 of them for the last round. The only step that also has a separate instruction is InvMixColumn Transformation (AESIMC). Why is that? On…
Aviv A.
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How to find out what instruction set architecture machine implements dynamically?

1) I would like to know if we could write a C program to know about the instruction set architecture of the machine. 2) How does the operating system figure out what Instruction Set Architecture(ISA) the computer runs on during installation? If the…
user2626445
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What does insn stand for?

I need to come up with an x86(-64) disassembler so I started reading the source code for objdump. After searching around a bit I'm in a file, 'ia64-asmtab.h'. Inside is a struct 'ia64_main_table': struct ia64_main_table { /* The entry in the…
BLUC
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Indirect/Indexed Addressing Mode

When the instruction LOAD 800 is fed I understand how the other values are loaded into the accumulator but I don't know how you get the results for indexed and indirect addressing.
user3221287
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GA Framework for Virtual Machines

Does anyone know of any .NET genetic algorithm frameworks for evolving instructions sets in virtual machines to solve abstract problems? I would be particularly interested in a framework which allows virtual machines to self propagate within a pool…
acheo
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What instruction sets are in the Piledriver architecture that are not in Bulldozer?

I write quite a bit of code in 64-bit x86_64 assembly language, and I am about to begin another large function library to provide all conventional bitwise, shift, logical, arithmetic, math operators and functions for s0128, s0256, s0512, s1024…
honestann
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How do assembly instruction differentiate between register, memory address, immediate value or offset parameter?

I've been wondering, are there some invisible op-codes or flags or anything that tells the assembly instruction how to treat its parameters? Am a little confused, since apparently the same instruction can operate with different type operands -…
user2341104
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How does the 68000 internally represent instructions?

How does the 68000 internally represent instructions. I've read that there are different types of instructions: single effective operation word format instructions, brief and full extension word format instructions. The single effective operation…
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why is there severals encodings for one instruction in ARMv7

I am currently trying to implement a disassembler for the ARM cortex A9, which implement the ARMv7 instruction set. For that I am using the manual "DDI0406C_b_arm_architecture_reference_manual.pdf" that can be download here (after having registered…
user2299676
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pdp8 mri instruction(s) on a page boundary

Does anyone know how the pdp8 hardware (and does it vary by model) handles the mri instructions on a page boundary. If your instruction is at address 0177 for example the program counter is used to read that instruction then increments essentially.…
old_timer
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instruction set emulator guide

I am interested in writing emulators like for gameboy and other handheld consoles, but I read the first step is to emulate the instruction set. I found a link here that said for beginners to emulate the Commodore 64 8-bit microprocessor, the thing…
hakuna matata
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Can i use the same ARM assembly for different ARM processors (Cortex,Tegra and so on)?

I'm interested if ARM assembly common for all types of ARM's? For example if I write some function in ARM assembly will it works the same on Cortex, Nvidia Tegra, Qualcomm etc? Can I use the same instruction set or SIMD engines or NEON on different…
Oleksandr Karaberov
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Why "execute" located before "memory" in Instruction Set Achitecture?

I have learnd Processor Architecture 3 years ago. Until today , I can't figure out why execute located before memory in the sequential instructions. While executing the instruction [ mov (%eax) %ebx] , does it needn't to access memory? Thanks!
wenwenhao
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