4

I have just learnt MIPS architecture in the class. I am reading other Instruction Set Architectures (ARM currently) and found some differences between ARM and MIPS. Both have different instruction formats, register set, etc.

Is there any difference in the data path of ARM from MIPS? because the data path involves fetching, decoding, and executing the instruction and it must be same for all Instruction Set Architectures.

I could not find the information about ARM data path from where I am reading this.

azhar baloch
  • 527
  • 6
  • 11
  • 1
    ARM and MIPS can both be implemented with different micro architectures (and they have been), so there are about as many differences as you want, depending on which pair of implementations you compare. – harold Apr 21 '17 at 20:23
  • 1
    One important difference is that ARM has a lot of conditional execution, while MIPS has delay slots. Also, ARM has a condition-register, which needs to be treated specially for decent performance. ARM also has fairly complicated addressing, pre-shifted arithmetic operations and sequenced load/store operations. OTOH, MIPS has a horrific multiply/divide unit that requires special casing. – EOF Apr 21 '17 at 20:31
  • @EOF would you please provide me any link from where I can know about ARM data path? I have tried a lot but could not find any helpful material. – azhar baloch Apr 21 '17 at 20:35
  • 1
    @azharbaloch Probably because there is not *one* "data path". You have an ISA specification that specifies the programmer's model, and you have *implementations* that use a microarchitecture that has (lots of) data paths. – EOF Apr 21 '17 at 20:38
  • @EOF but we have learnt only one kind of data path for MIPS, May there be other data paths for MIPS also? – azhar baloch Apr 21 '17 at 20:43
  • 1
    @azharbaloch You were probably taught a simplified model of a scalar in-order pipelined (five stage?) MIPS. The original ARM1 was a scalar in-order pipelined (three stages) design, but somewhat more complicated than MIPS. – EOF Apr 21 '17 at 20:46
  • 1
    @EOF One last question (sorry for distribution), If we consider the simplified model of a scalar in-order pipelined MIPS and ARM pipelined design, what will be the differences in data paths? suppose we consider only basic instructions such as ADD, LDR, SDR, and branch instructions. – azhar baloch Apr 21 '17 at 20:54
  • 1
    @azharbaloch In such a model ARM will tend to have a one cycle longer pipeline bubble on a mis-taken branch due to the lack of a delay slot. – EOF Apr 21 '17 at 20:58
  • and of course arm did a do-over with ARMv8, no more conditional execution on every instruction, a wasted 4 bits 12.5%...Mips doesnt have delay slots now, it is an optional legacy setting, you dont need to expose that to the customer anymore (never really did). Arms pipe is not two instructions ahead as the program counter implies, just an illusion as well. the conditional execution, sure, was to keep the pipe going, but with the other things that have happened, they dont really need to do this anymore (same goes for delay slots). – old_timer Apr 21 '17 at 22:57

2 Answers2

5

The MIPS you learned is no doubt an educational one from the text books (Patterson and Hennessey). The real MIPS cores as well as the ARM cores can/do vary from core to core, you can have multiple armv7-m cores that have a different implementation with respect to the pipeline stages. Note ARM and MIPS and RISC in general are not microcoded, dont allow x86 implementations affect your understanding.

So there is no one answer to this, and there is no one answer to what datapaths do MIPS processors use, what datapaths do ARM processors use with respect to fetch, decode, execute, writeback, ...

The CONCEPTS fetch, decode, execute, ... are used by all processors RISC or not, just how and when they do it varies, they can break down those steps into smaller steps and implement those in a longer pipe, or do them parallel and have a wider pipe.

For MIPS anything go to MIPS and download their documentation. for arm go to arm you want the architectural reference manual and the technical reference manual for a particular architecture family and specific core you are interested in. They have some new programmers manual or developers manual, skip that, or understand it is the above two manuals with holes in it. You may also want to get the amba/axi documentation to understand how the busses work, you could design an arm with a different bus, but it is educational if you were taught the traditional address bidirectional data, writes strobe, read strobe, chip enable type bus (which still lives on in wishbone a popular bus used in open cores and other places, a little more complicated but much closer to the old school bus).

old_timer
  • 69,149
  • 8
  • 89
  • 168
  • ARM32 is *heavily* microcoded today. You only have to look at the architecture manual to see lots of instructions that won't fit into a superscalar/OoO paradigm due to things like modifying multiple registers. Aarch64 cleans up the worst (LDM/STM, SMULL/UMULL, VTRN/VZIP/VUZP/VSWP...). – EOF Apr 22 '17 at 18:16
  • define: today, starting with which architecture do you think this happened? ldm/stm trivial to state machine, multiply, no microcoding needed for those pretty easy to implement. – old_timer Apr 22 '17 at 20:05
  • doesnt make sense would be a huge waste of real estate, multiple registers, superscaler dont require microcoding... – old_timer Apr 22 '17 at 20:09
2

Both are RISC (reduced instruction set architecture).

According to D.Patterson and L.Hennessy

The principal difference is that MIPS has more registers and ARM has more addressing modes. There is a similar core of instruction sets for arithmetic-logical and data transfer instructions for MIPS and ARM.

Unlike MIPS, ARM does not reserve a register to contain 0. Although MIPS has just three simple data addressing modes, ARM has nine.

Conditional branch

MIPS uses the contents of registers to evaluate conditional branches. ARM uses the traditional four condition code bits stored in the program status word: negative, zero, carry, and overflow. They can be set on any arithmetic or logical instruction; unlike earlier architectures, this setting is optional on each instruction. An explicit option leads to fewer problems in a pipelined implementation. ARM uses conditional branches to test condition codes to determine all possible unsigned and signed relations.[Computer Organization and design by D.Patterson and L.Hennessey]

I could not find the information about ARM data path from where I am reading this?

I recommend you the book Computer Organization and design by D.Patterson and L.Hennessey ARM edition.

Adam
  • 856
  • 2
  • 9
  • 18